Challenges to adopting adiabatic circuits for systems‐on‐a‐chip
Abstract Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow‐trans...
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| Language: | English |
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Wiley
2021-09-01
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| Series: | IET Circuits, Devices and Systems |
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| Online Access: | https://doi.org/10.1049/cds2.12053 |
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| author | Krishnan S. Rengarajan Saroj Mondal Ravindra Kapre |
| author_facet | Krishnan S. Rengarajan Saroj Mondal Ravindra Kapre |
| author_sort | Krishnan S. Rengarajan |
| collection | DOAJ |
| description | Abstract Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow‐transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive‐feedback adiabatic logic (PFAL), two‐level adiabatic logic (2‐LAL) and clocked adiabatic logic in 40 nm CMOS technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2‐LAL are presented. The problem with 2‐LAL multi‐input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context—a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions. |
| format | Article |
| id | doaj-art-167aa376c93f42388bcc789f11cb147b |
| institution | Kabale University |
| issn | 1751-858X 1751-8598 |
| language | English |
| publishDate | 2021-09-01 |
| publisher | Wiley |
| record_format | Article |
| series | IET Circuits, Devices and Systems |
| spelling | doaj-art-167aa376c93f42388bcc789f11cb147b2025-02-03T06:47:36ZengWileyIET Circuits, Devices and Systems1751-858X1751-85982021-09-0115658159310.1049/cds2.12053Challenges to adopting adiabatic circuits for systems‐on‐a‐chipKrishnan S. Rengarajan0Saroj Mondal1Ravindra Kapre2EEE Department BITS Pilani‐Hyderabad Campus Hyderabad IndiaEEE Department BITS Pilani‐Hyderabad Campus Hyderabad IndiaInfineon Technologies America (IFAM) San Jose California USAAbstract Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. The architecture of a pipeline of stages with slow‐transitioning clock phases demands the generation and distribution of clock phases precisely and efficiently. This power must be more than offset by the power saved by using adiabatic circuits. The problems in adiabatic logic circuits are described, and solutions are proposed to address them. Three published topologies are considered, namely positive‐feedback adiabatic logic (PFAL), two‐level adiabatic logic (2‐LAL) and clocked adiabatic logic in 40 nm CMOS technology at 100 MHz. New circuit ideas for complete level restore in PFAL and avoidance of floating nodes in 2‐LAL are presented. The problem with 2‐LAL multi‐input gates is published and solved for the first time here using a modified PFAL. The conclusion is that a 3X power savings in PFAL is about the best that can be achieved in an SoC context—a low return given the required investments in area and complexity. This should motivate the future discovery of more efficient solutions.https://doi.org/10.1049/cds2.12053clocksCMOS logic circuitslogic designlow‐power electronicssystem‐on‐chip |
| spellingShingle | Krishnan S. Rengarajan Saroj Mondal Ravindra Kapre Challenges to adopting adiabatic circuits for systems‐on‐a‐chip IET Circuits, Devices and Systems clocks CMOS logic circuits logic design low‐power electronics system‐on‐chip |
| title | Challenges to adopting adiabatic circuits for systems‐on‐a‐chip |
| title_full | Challenges to adopting adiabatic circuits for systems‐on‐a‐chip |
| title_fullStr | Challenges to adopting adiabatic circuits for systems‐on‐a‐chip |
| title_full_unstemmed | Challenges to adopting adiabatic circuits for systems‐on‐a‐chip |
| title_short | Challenges to adopting adiabatic circuits for systems‐on‐a‐chip |
| title_sort | challenges to adopting adiabatic circuits for systems on a chip |
| topic | clocks CMOS logic circuits logic design low‐power electronics system‐on‐chip |
| url | https://doi.org/10.1049/cds2.12053 |
| work_keys_str_mv | AT krishnansrengarajan challengestoadoptingadiabaticcircuitsforsystemsonachip AT sarojmondal challengestoadoptingadiabaticcircuitsforsystemsonachip AT ravindrakapre challengestoadoptingadiabaticcircuitsforsystemsonachip |