A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power
Performance optimization is a crucial aspect of enhancing the efficiency of electronic systems, and scaling is a primary method for achieving optimal performance while maintaining the integrity of system architecture. This paper introduces a novel algorithm for optimizing transistor sizing in static...
Saved in:
| Main Authors: | , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10833602/ |
| Tags: |
Add Tag
No Tags, Be the first to tag this record!
|
| _version_ | 1832592906752360448 |
|---|---|
| author | Sanket M. Mantrashetti Arunkumar P Chavan Prakash Pawar H. V. Ravish Aradhya Omkar S. Powar |
| author_facet | Sanket M. Mantrashetti Arunkumar P Chavan Prakash Pawar H. V. Ravish Aradhya Omkar S. Powar |
| author_sort | Sanket M. Mantrashetti |
| collection | DOAJ |
| description | Performance optimization is a crucial aspect of enhancing the efficiency of electronic systems, and scaling is a primary method for achieving optimal performance while maintaining the integrity of system architecture. This paper introduces a novel algorithm for optimizing transistor sizing in static random-access memory (SRAM) to enhance speed, improve Static Noise Margin (SNM), and reduce leakage power consumption. The SRAM is designed using 45 nm technology and operates at a supply voltage of 1.2 V. To validate the algorithm’s effectiveness, Monte Carlo simulations were conducted under varying process, voltage, and temperature conditions. The results demonstrate read access times of 11.17 ps (HIGH) and 9.97 ps (LOW), and write access times of 12.00 ps (HIGH) and 17.00 ps (LOW). The measured SNM values for the read, write, and hold states were 328.2 mV, 453.7 mV, and 452.3 mV, respectively. The inclusion of precharge and write driver circuits allows for a compact SRAM layout, occupying <inline-formula> <tex-math notation="LaTeX">$9.79~\mu $ </tex-math></inline-formula> m<sup>2</sup>, with the SRAM cell itself occupying <inline-formula> <tex-math notation="LaTeX">$4.1~\mu $ </tex-math></inline-formula> m<sup>2</sup>. Furthermore, the proposed SRAM design exhibits low leakage power consumption of 1.64 pW, demonstrating the efficiency and performance benefits of the optimized transistor sizing approach. |
| format | Article |
| id | doaj-art-0fcca4f27e1a4d1fb5acf77cf535309a |
| institution | Kabale University |
| issn | 2169-3536 |
| language | English |
| publishDate | 2025-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj-art-0fcca4f27e1a4d1fb5acf77cf535309a2025-01-21T00:01:27ZengIEEEIEEE Access2169-35362025-01-01139942995410.1109/ACCESS.2025.352733310833602A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage PowerSanket M. Mantrashetti0https://orcid.org/0009-0000-3961-2029Arunkumar P Chavan1https://orcid.org/0000-0001-8056-8795Prakash Pawar2H. V. Ravish Aradhya3Omkar S. Powar4https://orcid.org/0000-0003-4646-8787Department of Electronics and Communication Engineering, R. V. College of Engineering, Bengaluru, IndiaMMRFIC Technology Pvt Ltd., Bengaluru, IndiaDepartment of Electronics and Communication Engineering, Indian Institute of Information Technology Dharwad, Dharwad, IndiaDepartment of Electronics and Communication Engineering, R. V. College of Engineering, Bengaluru, IndiaDepartment of Biomedical Engineering, Manipal Institute of Technology, Manipal Academy of Higher Education, Manipal, Karnataka, IndiaPerformance optimization is a crucial aspect of enhancing the efficiency of electronic systems, and scaling is a primary method for achieving optimal performance while maintaining the integrity of system architecture. This paper introduces a novel algorithm for optimizing transistor sizing in static random-access memory (SRAM) to enhance speed, improve Static Noise Margin (SNM), and reduce leakage power consumption. The SRAM is designed using 45 nm technology and operates at a supply voltage of 1.2 V. To validate the algorithm’s effectiveness, Monte Carlo simulations were conducted under varying process, voltage, and temperature conditions. The results demonstrate read access times of 11.17 ps (HIGH) and 9.97 ps (LOW), and write access times of 12.00 ps (HIGH) and 17.00 ps (LOW). The measured SNM values for the read, write, and hold states were 328.2 mV, 453.7 mV, and 452.3 mV, respectively. The inclusion of precharge and write driver circuits allows for a compact SRAM layout, occupying <inline-formula> <tex-math notation="LaTeX">$9.79~\mu $ </tex-math></inline-formula> m<sup>2</sup>, with the SRAM cell itself occupying <inline-formula> <tex-math notation="LaTeX">$4.1~\mu $ </tex-math></inline-formula> m<sup>2</sup>. Furthermore, the proposed SRAM design exhibits low leakage power consumption of 1.64 pW, demonstrating the efficiency and performance benefits of the optimized transistor sizing approach.https://ieeexplore.ieee.org/document/10833602/Area efficientdesign optimizationleakage currentlow latencyMonte Carlo analysispower efficient |
| spellingShingle | Sanket M. Mantrashetti Arunkumar P Chavan Prakash Pawar H. V. Ravish Aradhya Omkar S. Powar A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power IEEE Access Area efficient design optimization leakage current low latency Monte Carlo analysis power efficient |
| title | A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power |
| title_full | A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power |
| title_fullStr | A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power |
| title_full_unstemmed | A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power |
| title_short | A Novel Algorithm for Aspect Ratio Estimation in SRAM Design to Achieve High SNM, High Speed, and Low Leakage Power |
| title_sort | novel algorithm for aspect ratio estimation in sram design to achieve high snm high speed and low leakage power |
| topic | Area efficient design optimization leakage current low latency Monte Carlo analysis power efficient |
| url | https://ieeexplore.ieee.org/document/10833602/ |
| work_keys_str_mv | AT sanketmmantrashetti anovelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT arunkumarpchavan anovelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT prakashpawar anovelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT hvravisharadhya anovelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT omkarspowar anovelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT sanketmmantrashetti novelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT arunkumarpchavan novelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT prakashpawar novelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT hvravisharadhya novelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower AT omkarspowar novelalgorithmforaspectratioestimationinsramdesigntoachievehighsnmhighspeedandlowleakagepower |