Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency
One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce...
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| Format: | Article |
| Language: | English |
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Wiley
2012-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2012/185784 |
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| _version_ | 1832554337187921920 |
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| author | Supriya Aggarwal Kavita Khare |
| author_facet | Supriya Aggarwal Kavita Khare |
| author_sort | Supriya Aggarwal |
| collection | DOAJ |
| description | One of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper. |
| format | Article |
| id | doaj-art-0c4ab4991f4a4d8b9c5ed590455850d9 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2012-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-0c4ab4991f4a4d8b9c5ed590455850d92025-02-03T05:51:41ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092012-01-01201210.1155/2012/185784185784Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and LatencySupriya Aggarwal0Kavita Khare1Department of Electronics and Communication Engineering, MANIT, Bhopal 462007, IndiaDepartment of Electronics and Communication Engineering, MANIT, Bhopal 462007, IndiaOne of the most important steps in spectral analysis is filtering, where window functions are generally used to design filters. In this paper, we modify the existing architecture for realizing the window functions using CORDIC processor. Firstly, we modify the conventional CORDIC algorithm to reduce its latency and area. The proposed CORDIC algorithm is completely scale-free for the range of convergence that spans the entire coordinate space. Secondly, we realize the window functions using a single CORDIC processor as against two serially connected CORDIC processors in existing technique, thus optimizing it for area and latency. The linear CORDIC processor is replaced by a shift-add network which drastically reduces the number of pipelining stages required in the existing design. The proposed design on an average requires approximately 64% less pipeline stages and saves up to 44.2% area. Currently, the processor is designed to implement Blackman windowing architecture, which with slight modifications can be extended to other widow functions as well. The details of the proposed architecture are discussed in the paper.http://dx.doi.org/10.1155/2012/185784 |
| spellingShingle | Supriya Aggarwal Kavita Khare Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency International Journal of Reconfigurable Computing |
| title | Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency |
| title_full | Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency |
| title_fullStr | Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency |
| title_full_unstemmed | Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency |
| title_short | Redesigned-Scale-Free CORDIC Algorithm Based FPGA Implementation of Window Functions to Minimize Area and Latency |
| title_sort | redesigned scale free cordic algorithm based fpga implementation of window functions to minimize area and latency |
| url | http://dx.doi.org/10.1155/2012/185784 |
| work_keys_str_mv | AT supriyaaggarwal redesignedscalefreecordicalgorithmbasedfpgaimplementationofwindowfunctionstominimizeareaandlatency AT kavitakhare redesignedscalefreecordicalgorithmbasedfpgaimplementationofwindowfunctionstominimizeareaandlatency |