The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units
This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It...
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| Format: | Article |
| Language: | English |
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Wiley
2008-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2008/736203 |
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| author | Chi Wai Yu Julien Lamoureux Steven J. E. Wilton Philip H. W. Leong Wayne Luk |
| author_facet | Chi Wai Yu Julien Lamoureux Steven J. E. Wilton Philip H. W. Leong Wayne Luk |
| author_sort | Chi Wai Yu |
| collection | DOAJ |
| description | This paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used. |
| format | Article |
| id | doaj-art-09c184a2816e49188bccd3777a7c9888 |
| institution | Kabale University |
| issn | 1687-7195 1687-7209 |
| language | English |
| publishDate | 2008-01-01 |
| publisher | Wiley |
| record_format | Article |
| series | International Journal of Reconfigurable Computing |
| spelling | doaj-art-09c184a2816e49188bccd3777a7c98882025-02-03T00:59:13ZengWileyInternational Journal of Reconfigurable Computing1687-71951687-72092008-01-01200810.1155/2008/736203736203The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic UnitsChi Wai Yu0Julien Lamoureux1Steven J. E. Wilton2Philip H. W. Leong3Wayne Luk4Department of Computing, Imperial College London, London SW7 2AZ, UKDepartment of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, V6T 1Z4, CanadaDepartment of Electrical and Computer Engineering, University of British Columbia, Vancouver, British Columbia, V6T 1Z4, CanadaDepartment of Computer Science and Engineering, Chinese University of Hong Kong, Hong KongDepartment of Computing, Imperial College London, London SW7 2AZ, UKThis paper examines the interface between fine-grained and coarse-grained programmable logic in FPGAs. Specifically, it presents an empirical study that covers the location, pin arrangement, and interconnect between embedded floating point units (FPUs) and the fine-grained logic fabric in FPGAs. It also studies this interface in FPGAs which contain both FPUs and embedded memories. The results show that (1) FPUs should have a square aspect ratio; (2) they should be positioned near the center of the FPGA; (3) their I/O pins should be arranged around all four sides of the FPU; (4) embedded memory should be located between the FPUs; and (5) connecting higher I/O density coarse-grained blocks increases the demand for routing resources. The hybrid FPGAs with embedded memory required 12% wider channels than the case where embedded memory is not used.http://dx.doi.org/10.1155/2008/736203 |
| spellingShingle | Chi Wai Yu Julien Lamoureux Steven J. E. Wilton Philip H. W. Leong Wayne Luk The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units International Journal of Reconfigurable Computing |
| title | The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units |
| title_full | The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units |
| title_fullStr | The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units |
| title_full_unstemmed | The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units |
| title_short | The Coarse-Grained/Fine-Grained Logic Interface in FPGAs with Embedded Floating-Point Arithmetic Units |
| title_sort | coarse grained fine grained logic interface in fpgas with embedded floating point arithmetic units |
| url | http://dx.doi.org/10.1155/2008/736203 |
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