Accelerating Deep Learning-Based Morphological Biometric Recognition with Field-Programmable Gate Arrays by Nourhan Zayed, Nahed Tawfik, Mervat M. A. Mahmoud, Ahmed Fawzy, Young-Im Cho, Mohamed S. Abdallah

“…To tackle these issues, it is essential to construct a system based on field-programmable gate arrays (FPGAs) to speed up CNNs. …”
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A Precise High Count-Rate FPGA Based Multi-Channel Coincidence Counting System for Quantum Photonics Applications by Ekin Arabul, Stefano Paesani, Scott Tancock, John Rarity, Naim Dahnoun

“…We are proposing a Field Programmable Gate Array (FPGA) based coincidence counting system which provides 8 operational channels with 8.9 ps root mean square (RMS) resolution (with a bin width of 7.7 ps) and a count-rate of 320 million counts per second (MCPS) (with 40 MCPS per channel). …”
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FPGA-Based Implementation of Size-Adaptive Privacy Amplification in Quantum Key Distribution by Shen-Shen Yang, Zeng-Liang Bai, Xu-Yang Wang, Yong-Min Li

“…The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. …”
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A High-Speed, Multi-Channel Lossless Compression Algorithm for High-Resolution Video on FPGA by Xingkai Du, Longhua Xie, Hongchuan Huang, Huawei Chen, Xiaolong Guo, Tingyu Zhao

“…This paper proposes a four-channel high-speed lossless compression algorithm based on FPGA (Field-Programmable Gate Array). The algorithm uses the difference between adjacent pixels, which has fewer data bit widths, to replace the original pixels for transmission. …”
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A Tree Crown Segmentation Approach for Unmanned Aerial Vehicle Remote Sensing Images on Field Programmable Gate Array (FPGA) Neural Network Accelerator by Jiayi Ma, Lingxiao Yan, Baozhe Chen, Li Zhang

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A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression by Xufeng Li, Li Zhou, Yan Zhu

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High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA by Lorenzo Castelvero, Ignacio H. Lopez Grande, Valerio Pruneri

“…In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). …”
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High-speed and reduced energy delay product TCAM on FPGA for network routers by Sridhar Raj Sankara Vadivel, Shantha Selvakumari Ramapackiam

“…The proposed work used six-input (RAM64X1S) LUTs in field-programmable gate arrays by allowing both search and update operations to be performed simultaneously during the data update in a particular LUT. …”
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Floating Point Multiple-Precision Fused Multiply Add Architecture for Deep Learning Computation on Artix 7 FPGA Board by VINOTHENI, M. S., JAWAHAR SENTHIL KUMAR, V.

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Design of an Encrypted Serial Communication System Based on Pseudo-random Sequences by LI Miao, FAN Linbin, WANG Yan

“…Within an environment of the communication system created by using field-programmable gate array (FPGA), experiments revealed the maximum baud rate at 20 Mbit/s, which could meet the encryption requirements of m-sequences of 4~15 series, and yielded good results.…”
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FPGA Implementation for 24.576-Gbit/s Optical PAM4 Signal Transmission with MLP-Based Digital Pre-Distortion by Sheng Hu, Tianqi Zheng, Chengzhen Bian, Xiongwei Yang, Xinda Sun, Zonghui Zhu, Yumeng Gou, Yuanxiao Meng, Jie Zhang, Jingtao Ge, Yichen Li, Kaihui Wang

“…In this work, an MLP-DPD scheme was implemented on a field-programmable gate array (FPGA). The FPGA was used to generate a 14.7456 GBaud pre-distorted pulse amplitude modulation 4-level (PAM4) signal. …”
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Parallelized Field-Programmable Gate Array Data Processing for High-Throughput Pulsed-Radar Systems by Aaron D. Pitcher, Mihail Georgiev, Natalia K. Nikolova, Nicola Nicolici

“…A parallelized field-programmable gate array (FPGA) architecture is proposed to realize an ultra-fast, compact, and low-cost dual-channel ultra-wideband (UWB) pulsed-radar system. …”
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Parallel multi‐rate simulation scheme for modular multilevel converter‐based high‐voltage direct current with accurate simulation of high‐frequency characteristics and field progra... by Chongru Liu, Yanqi Hou, Haoyun Dong, Yipeng Lv, Xinyan Wang, Chenbo Su

“…Secondly, the computing architectures of the primary system solver and modular multilevel converter controller are designed based on a field programmable gate array (FPGA). The real‐time simulation platform for a four‐terminal true bipolar MMC‐HVDC is constructed based on the FPGA array. …”
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A Dual Polyphase Decomposition Overlapped Polyphase Filter Bank and Its Implementation in a Field-programmable Gate Array by Shaocong Guo, Qiao Meng, Hailong Zhang, Yazhou Zhang, Chenye Zhou, Gaojing Li, Jie Wu, Jianxun Shao

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FASQuiC: Flexible Architecture for Scalable Spin Qubit Control by Mathieu Toubeix, Eric Guthmuller, Adrian Evans, Antoine Faurie, Tristan Meunier

“…The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. …”
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Scalable 5G NR Rate-Matcher and Rate-Dematcher for Efficient Use in FPGA Accelerators by Nemanja Filipovic, Dragomir El Mezeni, Vladimir L. Petrovic

“…Additionally, LDPC coding is tightly coupled with rate-matching. This paper presents novel hardware architectures of rate-matcher and rate-dematcher, targeting field programmable gate array (FPGA) RAN accelerators. …”
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Memory-Optimized Cubic Splines for High-Fidelity Quantum Operations by Jan Ole Ernst, Jan Snoeijs, Mitchell Peaks, Jochen Wolf

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Real-Time Implementation of Hybrid Visible Light/Infrared Communications Supporting Full-Range Dynamic Dimming Control by Shixin Liu, Xiaodi You, Jian Chen, Changyuan Yu, Chaoran Xiong, Mingyi Gao, Gangxiang Shen

“…Experimental results from implementation using field-programmable gate arrays (FPGA) demonstrate real-time transmission under precise full-range dimming control, dynamically ranging from 1 to 0 with a resolution of 0.0053, maintaining a consistent 10 Mb/s data rate at bit error rates (BERs) lower than 3.4 × 10^−4 and 20 Mb/s at BERs lower than 7.0 × 10^−3 within a link range of 0.53 m without light concentration at the transmitter. …”
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FPGA-Based Rate-Compatible LDPC Codes for the Next Generation of Optical Transmission Systems by Ding Zou, Ivan B. Djordjevic

“…In this paper, we propose a rate-compatible forward error-correcting (FEC) scheme based on low-density-parity check (LDPC) codes together with its software reconfigurable unified field-programmable gate array (FPGA) architecture. …”
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Ultrahigh-Performance Radio Frequency System-on-Chip Implementation of a Kalman Filter-Based High-Precision Time and Frequency Synchronization for Networked Integrated Sensing and... by Roghayeh Ghasemi, Patrick Fenske, Tobias Koegel, Markus Hehn, Ingrid Ullmann, Martin Vossiek

“…In this article, a novel real-time wireless time and frequency synchronization scheme is developed and fully implemented on a high-end radio frequency system-on-chip field-programmable gate array (FPGA) platform. The excellent performance and robustness of the proposed solution in practical applications are demonstrated. …”
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