Accelerating Deep Learning-Based Morphological Biometric Recognition with Field-Programmable Gate Arrays by Nourhan Zayed, Nahed Tawfik, Mervat M. A. Mahmoud, Ahmed Fawzy, Young-Im Cho, Mohamed S. Abdallah

“…To tackle these issues, it is essential to construct a system based on field-programmable gate arrays (FPGAs) to speed up CNNs. …”
Get full text

Parallelized Field-Programmable Gate Array Data Processing for High-Throughput Pulsed-Radar Systems by Aaron D. Pitcher, Mihail Georgiev, Natalia K. Nikolova, Nicola Nicolici

“…A parallelized field-programmable gate array (FPGA) architecture is proposed to realize an ultra-fast, compact, and low-cost dual-channel ultra-wideband (UWB) pulsed-radar system. …”
Get full text

A Precise High Count-Rate FPGA Based Multi-Channel Coincidence Counting System for Quantum Photonics Applications by Ekin Arabul, Stefano Paesani, Scott Tancock, John Rarity, Naim Dahnoun

“…We are proposing a Field Programmable Gate Array (FPGA) based coincidence counting system which provides 8 operational channels with 8.9 ps root mean square (RMS) resolution (with a bin width of 7.7 ps) and a count-rate of 320 million counts per second (MCPS) (with 40 MCPS per channel). …”
Get full text

Parallel multi‐rate simulation scheme for modular multilevel converter‐based high‐voltage direct current with accurate simulation of high‐frequency characteristics and field programmable gate array‐based implementation by Chongru Liu, Yanqi Hou, Haoyun Dong, Yipeng Lv, Xinyan Wang, Chenbo Su

“…Secondly, the computing architectures of the primary system solver and modular multilevel converter controller are designed based on a field programmable gate array (FPGA). The real‐time simulation platform for a four‐terminal true bipolar MMC‐HVDC is constructed based on the FPGA array. …”
Get full text

A Dual Polyphase Decomposition Overlapped Polyphase Filter Bank and Its Implementation in a Field-programmable Gate Array by Shaocong Guo, Qiao Meng, Hailong Zhang, Yazhou Zhang, Chenye Zhou, Gaojing Li, Jie Wu, Jianxun Shao

Get full text

A Tile-Based Multi-Core Hardware Architecture for Lossless Image Compression and Decompression by Xufeng Li, Li Zhou, Yan Zhu

Get full text

A Tree Crown Segmentation Approach for Unmanned Aerial Vehicle Remote Sensing Images on Field Programmable Gate Array (FPGA) Neural Network Accelerator by Jiayi Ma, Lingxiao Yan, Baozhe Chen, Li Zhang

Get full text

Design of an Encrypted Serial Communication System Based on Pseudo-random Sequences by LI Miao, FAN Linbin, WANG Yan

“…Within an environment of the communication system created by using field-programmable gate array (FPGA), experiments revealed the maximum baud rate at 20 Mbit/s, which could meet the encryption requirements of m-sequences of 4~15 series, and yielded good results.…”
Get full text

FPGA-Based Implementation of Size-Adaptive Privacy Amplification in Quantum Key Distribution by Shen-Shen Yang, Zeng-Liang Bai, Xu-Yang Wang, Yong-Min Li

“…The processing speed of the PA algorithm inevitably affects the final key rate of the QKD system. We propose a high-speed PA algorithm based on field-programmable gate array (FPGA), where the matrix multiplications are divided into a number of rhomboid-block operations. …”
Get full text

A High-Speed, Multi-Channel Lossless Compression Algorithm for High-Resolution Video on FPGA by Xingkai Du, Longhua Xie, Hongchuan Huang, Huawei Chen, Xiaolong Guo, Tingyu Zhao

“…This paper proposes a four-channel high-speed lossless compression algorithm based on FPGA (Field-Programmable Gate Array). The algorithm uses the difference between adjacent pixels, which has fewer data bit widths, to replace the original pixels for transmission. …”
Get full text

Multi-Node All-Optical Interconnect Network Routing for Data-Center Parallel Computers by Shuailong Yang, Liu Yang, Fengguang Luo, Biyu You, Yao Ni, Danhui Chen

Get full text

High Throughput 512Mbps True Random Number Generation Using Uncertainty in Mobile Communication Bands by Farid Alidoust Aghdam, Mohammad Erfanimehr, Hodjat Ahmadi, Armin Zarghami, Seyed Ahmad Madani, Ali Rostami

“…The captured data is then processed using a field-programmable gate array to generate high-quality true random numbers. …”
Get full text

Floating Point Multiple-Precision Fused Multiply Add Architecture for Deep Learning Computation on Artix 7 FPGA Board by VINOTHENI, M. S., JAWAHAR SENTHIL KUMAR, V.

Get full text

PLORC: A Pipelined Lossless Reference-Free Compression Architecture for FASTQ Files by Haori Zheng, Jietao Chen, Feng Yu, Weijie Chen

“…The proposed PLORC architecture consists of several submodules optimized for the structure of FASTQ files, maintaining the balance between the compression ratio (CR) and throughput rate (TPR). To verify the PLORC architecture in hardware, we implemented the PLORC compressor and decompressor in FPGA (field-programmable gate array). …”
Get full text

Dynamically tuneable pre‐modulation filter for an airborne PCM/FM telemetry system by Sudarsana Reddy Karnati, Lakshmi Bopanna, Dhanunjay R Jahagirdar

Get full text

High-Performance Time-to-Digital Conversion on a 16-nm Ultrascale+ FPGA by Lorenzo Castelvero, Ignacio H. Lopez Grande, Valerio Pruneri

“…In recent years, field-programmable gate arrays (FPGAs) have emerged as promising platforms for implementing picosecond-resolution time-to-digital converters (TDCs). …”
Get full text

FASQuiC: Flexible Architecture for Scalable Spin Qubit Control by Mathieu Toubeix, Eric Guthmuller, Adrian Evans, Antoine Faurie, Tristan Meunier

“…The architecture can produce programmable combinations of ramps, frequency combs, and arbitrary waveform generation (AWG) at 5 GS/s, with a worst-case digital feedback latency of 76.8 ns. The field-programmable gate array (FPGA)-based system is highly configurable and takes advantage of bitstream switching to achieve the high flexibility required for scalable calibration. …”
Get full text

High-speed and reduced energy delay product TCAM on FPGA for network routers by Sridhar Raj Sankara Vadivel, Shantha Selvakumari Ramapackiam

“…The proposed work used six-input (RAM64X1S) LUTs in field-programmable gate arrays by allowing both search and update operations to be performed simultaneously during the data update in a particular LUT. …”
Get full text

Memory-Optimized Cubic Splines for High-Fidelity Quantum Operations by Jan Ole Ernst, Jan Snoeijs, Mitchell Peaks, Jochen Wolf

“…We show an optimized implementation of this strategy, using a two-stage curve-fitting process and additional symmetry operations to load a high-sampling pulse output on an field-programmable gate array. This results in a favorable accuracy-versus-memory-footprint tradeoff. …”
Get full text

FPGA Implementation for 24.576-Gbit/s Optical PAM4 Signal Transmission with MLP-Based Digital Pre-Distortion by Sheng Hu, Tianqi Zheng, Chengzhen Bian, Xiongwei Yang, Xinda Sun, Zonghui Zhu, Yumeng Gou, Yuanxiao Meng, Jie Zhang, Jingtao Ge, Yichen Li, Kaihui Wang

“…In this work, an MLP-DPD scheme was implemented on a field-programmable gate array (FPGA). The FPGA was used to generate a 14.7456 GBaud pre-distorted pulse amplitude modulation 4-level (PAM4) signal. …”
Get full text