Design of a Demodulation Algorithm for UWOC based on Improved Manchester Coding by ZHANG You, HU Fangren, ZHAO Xiaoyan, ZHOU Jun, WANG Qilong

“…The algorithm is designed and implemented on a Field Programmable Gate Array (FPGA), and a UWOC system using this method is built to conduct BER tests under different environments and distances.…”
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Real-Time 262-Mb/s Visible Light Communication With Digital Predistortion Waveform Shaping by Weishu Xu, Min Zhang, Dahai Han, Zabih Ghassemlooy, Pengfei Luo, Yongjian Zhang

“…The proposed scheme is implemented on a field-programmable gate array (FPGA) and a digital-to-analog converter based test bed, which is flexible and reconfigurable by programming the FPGA to match different LED characteristics and varied data rates. …”
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Design and development of SHINE accelerator fast interlock system by YU Chunlei, CHEN Guanghua, DING Jianguo, LI Ming, XIAO Qingwen, YAN Yingbing

“…Due to 1 MHz repetition rate and thousands of kilometers length of SHINE, the accelerator interlock system should be a large system with response speed in microsecond magnitude and capable of processing tens of thousands of signals simultaneously.PurposeThis study aims to design and implement fast interlock system integrated with the conventional slow interlock system for SHINE accelerator.MethodThrough the analysis of SHINE requirements, FPGA (Field Programmable Gate Array) technology, distributed control technology, and network communication technology were adopted to complete the design of the fast interlock system. …”
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A Multi-Class ECG Signal Classifier Using a Binarized Depthwise Separable CNN with the Merged Convolution–Pooling Method by Rui Zhang, Ranran Zhou, Zuting Zhong, Haifeng Qi, Yong Wang

“…The proposed bDSCNN model is evaluated on an Intel DE1-SoC field-programmable gate array (FPGA), and the experimental results demonstrate that the proposed system achieves a five-class classification accuracy of 96.61% and a macro-F1 score of 89.08%, along with a dynamic power dissipation of 20 μW for five-category ECG signal classification. …”
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Real-Time Water-to-Air Communication System Under Dynamic Water Surface and Strong Background Radiation by Tianrui Lin, Tianjian Wei, Qingqing Hu, Chunfang Fu, Nuo Huang, Xinhui Liu, Li Tang, Liang Su, Jianghua Luo, Chen Gong

“…This work explores water-to-air optical wireless communication (W2A-OWC) transmission schemes and realizes a prototype of real-time W2A-OWC system based on field programmable gate array. This prototype comprises underwater nodes, aerial nodes, and transmitter-receiver hardware circuits. …”
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Real-Time 14-Gbps Physical Random Bit Generator Based on Time-Interleaved Sampling of Broadband White Chaos by Longsheng Wang, Tong Zhao, Daming Wang, Danyu Wu, Lei Zhou, Jin Wu, Xinyu Liu, Yuncai Wang, Anbang Wang

“…After real-time interleaving combination and exclusive-OR operation in the field-programmable gate array (FPGA), a 14-Gbps binary stream with verified randomness is achieved.…”
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Design of a Multi-Node Data Acquisition System for Logging-While-Drilling Acoustic Logging Instruments Based on FPGA by Zhenyu Qin, Junqiang Lu, Baiyong Men, Shijie Wei, Jiakang Pan

“…The multi-node acquisition system is composed primarily of a main control circuit board and several acquisition circuit boards, all connected via an RS485 bus. The Field-Programmable Gate Array (FPGA) is utilized to develop the acquisition circuit board’s firmware, offering adjustable control over parameters, such as the AD7380’s operational mode, sampling rate, and depth, facilitating real-time and concurrent acquisition and storage of formation acoustic signals. …”
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HyperSense: Hyperdimensional Intelligent Sensing for Energy‐Efficient Sparse Data Processing by Sanggeon Yun, Hanning Chen, Ryozo Masukawa, Hamza Errahmouni Barkam, Andrew Ding, Wenjun Huang, Arghavan Rezvani, Shaahin Angizi, Mohsen Imani

“…Hardware‐wise, the field programmable gate array‐based domain‐specific accelerator tailored for HyperSense achieves a 5.6× speedup compared to YOLOv4 on NVIDIA Jetson Orin while showing up to 92.1% energy saving compared to the conventional system. …”
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Research on Two-Stage Data Compression at the Acquisition Node in Remote-Detection Acoustic Logging by Xiaolong Hao, Yangtao Hu, Bingnan Yan, Hang Hui, Yunxia Chen, Bingqi Zhang

“…This approach includes a field programmable gate array (FPGA)-based hardware system and a two-stage downhole data compression algorithm combining wavelet transform and adaptive differential pulse-code modulation paired with ground decompression software. …”
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Demonstration of a 2.34 Gbit/s Real-Time Single Silicon-Substrate Blue LED-Based Underwater VLC System by Ming Chen, Peng Zou, Long Zhang, Nan Chi

“…We develop a real-time discrete multi-tone (DMT) transceiver based on field programmable gate array (FPGA) chips for a single chip silicon-substrate light-emitting diode (LED) based underwater visible light communication (UVLC). …”
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High-Precision and Low-Complexity Symbol Synchronization Algorithm Based on Dual-Threshold Amplitude Decision for Real-Time IMDD OFDM-PON by Junjie Peng, You Sun, Haoshuo Chen, Tingting Xu, Zhengxuan Li, Qianwu Zhang, Junjie Zhang

“…We propose a low-complexity and high-precision symbol synchronization algorithm based on dual-threshold amplitude decision for field programmable gate array-based real-time intensity modulation direct detection orthogonal frequency division multiplexing-passive optical network (OFDM-PON) system. …”
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Design and Implementation of a High-Reliability Underwater Wireless Optical Communication System Based on FPGA by Tengfei Han, Peng Ding, Nan Liu, Zhengguang Wang, Zhenyao Li, Zhanqiang Ru, Helun Song, Zhizhen Yin

“…At the receiver, a fully digital automatic gain control (AGC) module, implemented on a field-programmable gate array (FPGA), is designed to mitigate signal fluctuations induced by underwater turbulence. …”
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SMART DShot: Secure Machine-Learning-Based Adaptive Real-Time Timing Correction by Hyunmin Kim, Zahid Basha Shaik Kadu, Kyusuk Han

“…Through comprehensive evaluation encompassing 32,000 Monte Carlo test iterations (500 per scenario × 16 scenarios × 4 algorithms) across 16 distinct operational scenarios and PolarFire SoC Field-Programmable Gate Array (FPGA) implementation, we demonstrate exceptional performance with 88.3% attack detection rate, only 2.3% false positive incidence, and substantial vulnerability mitigation reducing Common Vulnerability Scoring System (CVSS) severity from High (7.3) to Low (3.1). …”
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Performance of digital filtering and synchronization method for APD communication receiver by Hui-Jun Zhang, Peng Lin, Tong Wang, Zi-Qi Zhang, Bai-Qiu Zhao, Wen-Fang Jiao, Xiao-Nan Yu

“…The proposed algorithm was implemented and verified using a field-programmable gate array. Experiments conducted in an indoor OW communication environment demonstrate that the proposed algorithm significantly improves the detection sensitivity by approximately 6 ​dB and 5 ​dB at communication rates of 3.5 Mbps and 5.0 Mbps, respectively. …”
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Noise properties of preamplifier to be used with LN₂-cooled HgCdTe photodetector by Dmitry V. Kazantsev, Elena A. Kazantseva

“…The card has four 16-bit ADCs of sampling rate up to 25MSpS, a Spartan-3 field-programmable gate array controlling them, a TMS320C6713 processor, and RAM, in order to transmit the collected digital data to the motherboard through a common PCI-X slot. …”
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An Integrated Lightweight Neural Network Design and FPGA-Accelerated Edge Computing for Chili Pepper Variety and Origin Identification via an E-Nose by Ziyu Guo, Yong Yin, Haolin Gu, Guihua Peng, Xueya Wang, Ju Chen, Jia Yan

“…A chili pepper variety and origin detection system that integrates a field-programmable gate array (FPGA) with an electronic nose (e-nose) is proposed in this paper to address the issues of variety confusion and origin ambiguity in the chili pepper market. …”
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DA-FIS: A high-speed dynamic adaptive fault injection server framework for reliable FPGA-based embedded systems by Fatimah Alhayan, Gaganjot Kaur, Sultan Alanazi, Mohammed Burhanur Rehman, Wahida Mansouri, Da’ad Albalawneh, Ali Alqazzaz, Hanadi Alkhudhayr

“…Fault injection is a critical technique for assessing the reliability of field programmable gate array (FPGA)-based embedded systems, particularly in radiation-prone and safety-critical applications. …”
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A Pre-Selection–Enhanced Arbiter PUF for Strengthening PUF-Based Authentication by Rizka Reza Pahlevi, Hirokazu Hasegawa, Yukiko Yamaguchi, Hajime Shimada

“…We evaluate our design via a two-step methodology: an initial screening on a subset of boards, followed by a comprehensive assessment on 56 Field Programmable Gate Arrays (FPGA) boards—yielding 336 million challenge-response pairs (CRPs). …”
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Exploring Nutrient Deficiencies in Lettuce Crops: Utilizing Advanced Multidimensional Image Analysis for Precision Diagnosis by Jilong Xie, Shanshan Lv, Xihai Zhang, Weixian Song, Xinyi Liu, Yinghui Lu

“…To address these issues, this study developed a lettuce nutrient deficiency detection system using multi-dimensional image analysis and Field-Programmable Gate Arrays (FPGA). The system first applied a dynamic window histogram median filtering algorithm to denoise captured lettuce images. …”
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Parameter Justification of a Signal Recognition Algorithm Based on Detection at Two Intermediate Frequencies by Tran Huu Nghi, A. S. Podstrigaev, Nguyen Trong Nhan, D. A. Ikonenko

“…Due to the relative simplicity of transformations, this algorithm is implemented on commercially available field programmable gate arrays and allows processing received signals in near real-time. …”
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