Real-Time Implementation of Hybrid Visible Light/Infrared Communications Supporting Full-Range Dynamic Dimming Control by Shixin Liu, Xiaodi You, Jian Chen, Changyuan Yu, Chaoran Xiong, Mingyi Gao, Gangxiang Shen

“…Experimental results from implementation using field-programmable gate arrays (FPGA) demonstrate real-time transmission under precise full-range dimming control, dynamically ranging from 1 to 0 with a resolution of 0.0053, maintaining a consistent 10 Mb/s data rate at bit error rates (BERs) lower than 3.4 × 10^−4 and 20 Mb/s at BERs lower than 7.0 × 10^−3 within a link range of 0.53 m without light concentration at the transmitter. …”
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Ultrahigh-Performance Radio Frequency System-on-Chip Implementation of a Kalman Filter-Based High-Precision Time and Frequency Synchronization for Networked Integrated Sensing and... by Roghayeh Ghasemi, Patrick Fenske, Tobias Koegel, Markus Hehn, Ingrid Ullmann, Martin Vossiek

“…In this article, a novel real-time wireless time and frequency synchronization scheme is developed and fully implemented on a high-end radio frequency system-on-chip field-programmable gate array (FPGA) platform. The excellent performance and robustness of the proposed solution in practical applications are demonstrated. …”
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Scalable 5G NR Rate-Matcher and Rate-Dematcher for Efficient Use in FPGA Accelerators by Nemanja Filipovic, Dragomir El Mezeni, Vladimir L. Petrovic

“…Additionally, LDPC coding is tightly coupled with rate-matching. This paper presents novel hardware architectures of rate-matcher and rate-dematcher, targeting field programmable gate array (FPGA) RAN accelerators. …”
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Frequency-Modulated Antipodal Chaos Shift Keying Chaotic Communication on Field Program Gate Array: Prototype Design and Performance Insights by Filips Capligns, Ruslans Babajans, Darja Cirjulina, Deniss Kolosovs, Anna Litvinenko

“…A prototype of a frequency-modulated antipodal chaos shift keying (FM-ACSK) system is implemented on an Intel Cyclone V field-programmable gate array (FPGA) along with a complete mathematical model using Matlab R2022a Simulink software. …”
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FPGA-Based Rate-Compatible LDPC Codes for the Next Generation of Optical Transmission Systems by Ding Zou, Ivan B. Djordjevic

“…In this paper, we propose a rate-compatible forward error-correcting (FEC) scheme based on low-density-parity check (LDPC) codes together with its software reconfigurable unified field-programmable gate array (FPGA) architecture. …”
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A novel low complexity, low latency rate 1/2 FEC code by Maan A.S. Al-Adwany, Mohammed H. Al-Jammas, Hind Th. Hamdoon

“…Furthermore, the proposed code and the CC have been implemented on an Field Programmable Gate Array (FPGA) platform to evaluate the overhead in terms of usability of hardware resources. …”
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Characteristics and Mechanisms of Single Event Effects Caused by Atmospheric Neutrons in System in Package Device by YE Jiefeng1, 2, LIANG Chaohui2, ZHANG Zhangang2, ZHENG Shunshun1, 2, LEI Zhifeng2, LIU Zhili3, GENG Gaoying3, HAN Hui1

“…SEUs are found in the static random access memory (SRAM) module of the digital signal processor (DSP) and the block random access memory (BRAM) module inside the field programmable gate array (FPGA). SEFI errors are primarily program crashes and DSP state machine freezes. …”
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Velocity Signal Measurement Based on FPGA by LI Hui, LUO Zhengyu, XU Juan

“…In order to reduce CPU resource occupancy rate and the software complexity for velocity measuring, a FPGA(Field Programmable Gate Array) technology to measure velocity and related information was adopted as a supplement of CPU. …”
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Research on electromagnetic relay forwarding bidirectional transmission technology while drilling by LI Shiyin, ZHANG Bowen, ZHANG Guanjie, ZHANG Zhi, QI Huayan, WANG Bo

“…A drilling prototype, composed of field programmable gate array (FPGA), amplification circuit, analog-to-digital converter (ADC), digital-to-analog converter (DAC), and antenna, was constructed and tested. …”
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Evaluation system of high-speed anolog to digital converter based on FPGA by Chen Minqi, Deng Lanqing, Yang Linyun

“…A　high speed anolog to digital converter (ADC) evaluation system based on field programmable logic array (FPGA) is designed and implemented. …”
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Measurement Approaches and Implementation of a Fading Characterization Tester for Evaluating Optical Turbulent Channels by Yatian Li, Tianwen Geng, Xueliang Li, Ye Wang, Shijie Gao

“…Then a fading characterization tester (FCT) having these functions is implemented based on a field programmable gate array (FPGA). Our indoor experiment reveals the measurement accuracy of the FCT by comparing the measured results with the derived theoretical ones. …”
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Count Loss Evaluation for Accuracy Enhancement of a FPGA-Based Gamma Spectroscopy by Hoai-Phuong Pham, Viet-Huy Le, The-Dat Trang, Nhi-Dien Nguyen

“…A real-time digital multichannel analyzer based on a field-programmable gate array was commissioned subsequently to the detector’s preamplifier, and its performance is comparable to a commercial gamma spectroscopy. …”
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Fuzzy Matching Template Attacks on Multivariate Cryptography: A Case Study by Weijian Li, Xian Huang, Huimin Zhao, Guoliang Xie, Fuxiang Lu

“…Using QUAD for a case study, which is a typical multivariate cryptosystem with provable security, we perform our attack against both serial and parallel QUAD implementations on field programmable gate array (FPGA). Experimental results show that our attacks on both serial and parallel implementations require only about 30 and 150 power traces, respectively, to successfully reveal the secret key with a success rate close to 100%. …”
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Efficient reconfigurable regions management method for adaptive and dynamic FPGA based systems by Marwa Hannachi, Abdesslam B. Abdelali, Hassan Rabah, Abdellatif Mtibaa

“… Adaptive systems based on field programmable gate array (FPGA) architectures can greatly benefit from the high degree of flexibility offered by dynamic partial reconfiguration (DPR). …”
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Single Subcarrier Gold Sequences Modulated Timing Synchronization for Upstream OFDMA-PON by Xizhen Peng, Jian Chen, Yingchun Li, Yingxiong Song

“…The intensity-modulation and direct-detection real-time experimental demonstrations are carried out over 25-km standard SMF, the performance of the synchronization is investigated by using two optical network units (ONUs) and one optical line terminal based on field-programmable gate array. The results show that the accurate timing symbol synchronization can be achieved at received optical power as low as −21 dBm on the condition of sampling frequency offset range from 0 to 70 ppm between two ONUs. …”
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FPGA-Based Real-Time Moving Target Detection System for Unmanned Aerial Vehicle Application by Jia Wei Tang, Nasir Shaikh-Husin, Usman Ullah Sheikh, M. N. Marsono

“…The complex detection algorithm can be implemented in a real-time embedded system using Field Programmable Gate Array (FPGA). This paper presents the development of real-time moving target detection System-on-Chip (SoC) using FPGA for deployment on a UAV. …”
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High-Fidelity and High-Efficiency Digital Class-D Audio Power Amplifier by Cong Wei, Jianhan Wu, Rongshan Wei, Minghua He

“…The audio DAC, which is based on a field-programmable gate array, consumes 0.128 W and uses 7100 LUTs, which achieves 11.2% of the resource utilization rate. …”
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An Efficiency Multiplexing Scheme and Improved Sampling Method for Multichannel Data Acquisition System by Chengqun Chu, Yongfeng Ren, Xin Liu, Yongqiu Zheng, Wei Fang

“…All the technology of implementing the method is by using a low-cost field programmable gate array (FPGA). A sampling lookup table is built by the rule-based synchronous sampling frame structure for the input analogue multiplexers and stored into the internal block RAM resource in the FPGA to reduce the internal wiring resources and optimize the utilization. …”
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Hardware-Accelerated Data Readout Platform Using Heterogeneous Computing for DNA Data Storage by Xiaopeng Gou, Qi Ge, Quan Guo, Menghui Ren, Tingting Qi, Rui Qin, Weigang Chen

“…Here, we propose a novel heterogeneous computing architecture based on a field-programmable gate array (FPGA) to accelerate DNA data readout. …”
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Studies and Rejection of Intercrystal Crosstalk on FPGA in a High-Energy Photon-Counting System by Jiahao Chang, Huaxia Zhang, Shibo Jiang, Zhifang Wu, Shuo Xu

“…To suppress the crosstalk phenomenon, a field-programmable gate array (FPGA)-based algorithm is proposed to suppress inter-crystal scattering events, characterized by a time window of 5 nanoseconds and detector window sizes of one or two. …”
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