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    Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs by Shahnam Mirzaei, Ryan Kastner, Anup Hosangadi

    Published 2010-01-01
    “…The optimization target platforms are Xilinx Virtex FPGA devices where we compare the implementation results with those produced by Xilinx Coregen, which is based on distributed arithmetic (DA). …”
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