A radix‐8 modulo 2n multiplier using area and power‐optimized hard multiple generator by Naveen Kr. Kabra, Zuber M. Patel

“…Abstract The moduli 2n multiplier plays a vital role in the design of a residue number system processor. When the radix‐8 booth‐encoded technique is adopted to design this kind of multipliers, the hard multiple generator is crucial in terms of area, power, and delay. …”
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Design of 10T SRAM cell with improved read performance and expanded write margin by Ashish Sachdeva, V. K. Tomar

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Fully Integrated Chen Chaotic Oscillation System by Ziyi Ouyang, Jie Jin, Fei Yu, Long Chen, Lei Ding

“…The fully integrated Chen chaotic oscillation system is verified using Cadence IC Design Tools, and the post-layout simulation results indicate that the presented integrated Chen chaotic oscillation system only consumes 148 mW from ± 2.5 V supply voltage, and its chip area is 6.15 mm2.…”
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Fully Integrated Memristor and Its Application on the Scroll-Controllable Hyperchaotic System by Jie Jin, Li Cui

“…The fully integrated memristor and memristor-based hyperchaotic system are verified with the GlobalFoundries’ 0.18 μm CMOS process using Cadence IC Design Tools. …”
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A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model by Vassilis Alimisis, Dimitrios G. Arnaoutoglou, Emmanouil Anastasios Serlis, Argyro Kamperi, Konstantinos Metaxas, George A. Kyriacou, Paul P. Sotiriadis

“…The architectures were trained using Python and were compared to software-based classifiers. The circuit designs were executed using TSMC’s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.…”
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Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs by Shahnam Mirzaei, Ryan Kastner, Anup Hosangadi

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Energy-efficient analog-domain aggregator circuit for RRAM-based neural network accelerators by Khaled Humood, Yihan Pan, Shiwei Wang, Alexander Serb, Themis Prodromakis

“…In this work, we introduce a novel energy-efficient analog domain aggregator system designed for RRAM-based CIM systems. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulations and analysis. …”
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