CUDT: A CUDA Based Decision Tree Algorithm by Win-Tsung Lo, Yue-Shan Chang, Ruey-Kai Sheu, Chun-Chieh Chiu, Shyan-Ming Yuan

“…In the proposed system, CPU is responsible for flow control while the GPU is responsible for computation. …”
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HIGH-PERFORMANCE SIMULATIONS OF POPULATION-GENETIC PROCESSES IN BACTERIAL COMMUNITIES USING THE HAPLOID EVOLUTIONARY CONSTRUCTOR SOFTWARE by Z. S. Mustafin, Yu. G. Matushkin, S. A. Lashin

“…These high-performance versions are to be run on systems with shared and distributed memory, using CPU and/or GPU. Almost linear acceleration has been achieved on clusters and multi-core CPU. …”
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Accelerated computational implementation of reconciliation for continuous variable quantum key distribution on GPU by Shao-ting LIU, Xiao-kai WANG, Da-bo GUO

“…For the low computing speed of reconciliation for current continuous variable quantum key distribution， CPU＆amp;GPU-parallel reconciliation algorithms was designed based on LDPC of SEC protocol to speed up decoding computing.In order to raise decoding speed without sacrifice reconciliation efficiency,a static two-way cross linked list to efficiently store large scale sparse parity matrix was employed.The simulation experimental results show that the speed of the decoding rate reaches 16.4 kbit/s when the channel SNR is over 4.9 dB and the reliability of the 2×10⁵continuous variable quantum sequence,with reconciliation efficiency of 91.71%.The experimental based on the Geforce GT 650 MB GPU and the 2.5 GHz and 8 GB memory CPU hardware platform.Relative to the only CPU platform,computing speed increased by more than 15 times.…”
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An Efficient GPU-Accelerated Algorithm for Solving Dynamic Response of Fluid-Saturated Porous Media by Wancang Lin, Qinglong Zhou, Xinyi Chen, Wenhao Shi, Jie Ai

“…For a data set with two million degrees of freedom, it takes only about 0.05 s to compute an iterative step and transfer the data to the CPU. The program is designed to calculate either in single or double precision. …”
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Approximate Solutions of Delay Differential Equations with Constant and Variable Coefficients by the Enhanced Multistage Homotopy Perturbation Method by D. Olvera, A. Elías-Zúñiga, L. N. López de Lacalle, C. A. Rodríguez

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Optimization of Hydraulic Machinery Bladings by Multilevel CFD Techniques by Susanne Thum, Rudolf Schilling

“…The numerical design optimization for complex hydraulic machinery bladings requires a high number of design parameters and the use of a precise CFD solver yielding high computational costs. …”
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Refactoring Android Source Code Smells From Android Applications by Muhammad Fawad, Ghulam Rasool, Muhammad Bilal Riaz

“…This study enhances the Android application development lifecycle by offering developers a feasible solution for optimizing CPU efficiency, reducing memory use, and minimizing battery consumption.…”
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LE-YOLOv5: A Lightweight and Efficient Neural Network for Steel Surface Defect Detection by Chengshun Zhu, Yong Sun, Hongji Zhang, Shilong Yuan, Hui Zhang

“…At the same time, under the condition that the inference time for an image on a CPU-dependent low computing power force remains the same, the accuracy has improved by 5.3% compared to YOLOv8. …”
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FCM Clustering Approach Optimization Using Parallel High-Speed Intel FPGA Technology by Abedalmuhdi Almomany, Amin Jarrah, Anwar Al Assaf

“…Our experimental results (based on several datasets) show that the proposed method makes the FCM execution time more than 186 times faster than the conventional design running on a single-core CPU platform. Also, its processing power reached 89 giga floating points operations per second (GFLOPs).…”
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Parallel orchestration and deployment system for scalable heterogeneous service function chain supporting polymorphic network by Hao CHEN, Yuan YANG, Mingwei XU, Dan PEI, Yilin YOU

“…Aiming at the problem of second-level service function chain orchestration and deployment in the polymorphic data center with the scale of 10 000 servers, a scalable heterogeneous SFC parallel orchestration and deployment (SHOD) system was proposed.The scale-out orchestration time of service chain was reduced to seconds by partitioning the data center and adopting a parallel orchestrator design that minimizes resource usage.Using a mediator design model that satisfies the single-responsibility principle, the heterogeneous equipment scalable orchestration and deployment were realized as well as service function chain building chain.Experimental results show that in a data center with 10 000 servers, the scale-out orchestration time of SHOD system is reduced to <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <mfrac> <mn>1</mn> <mrow> <mn>12</mn></mrow> </mfrac> </math></inline-formula> of the existing system-Daisy, while only 1.5 times CPU utilization overhead is introduced.…”
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Analysis of DoS attacks on Docker inter-component stdio copy by Tianyu ZHOU, Wenbo SHEN, Nanzi YANG, Jinku LI, Chenggang QIN, Wang YU

“…In recent years,Docker has been widely deployed due to its flexibility and high scalability.However,its modular design leads to the DoS attacks on inter-component communication.A new DoS attack that outputs to stdout,causing high CPU usages among different Docker components.Analysis shows that the stdout output triggers the goroutines of Docker components.To find all goroutines setup paths,using the static analysis method to analyze the Docker components systematically was proposed.A static analysis framework was designed and implemented,and evaluated on Docker source code.The results show that static analysis framework finds 34 paths successfully,while 22 of them are confirmed by runtime verification.…”
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Multi-Softcore Architecture on FPGA by Mouna Baklouti, Mohamed Abid

“…The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. …”
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RP-Ring: A Heterogeneous Multi-FPGA Accelerator by Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin

“…Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.…”
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Research on LEO Satellite Network Routing Security by Wenhao XUE, Tian PAN, Chengcheng LU, Fan YANG, Tao HUANG, Yunjie LIU

“…The design of secure mechanisms and failure recovery mechanisms for inter-satellite routing has become pivotal in maintaining dependable communication within the LEO satellite network.To address the potential security threats faced by satellite networks, the impact of different routing attack behaviors on a typical inter-satellite routing protocol was analyzed and differentiated packet security authentication mechanisms and link failure recovery mechanisms were designed.Additionally, a satellite network emulation platform based on virtualization technology was constructed, enabled the verification of the effectiveness of the designed inter-satellite routing security mechanisms through the emulation of various routing attack scenarios.Furthermore, performance metrics such as CPU utilization and packet processing time were also evaluated before and after the introduction of security mechanisms.Experimental results demonstrated that the proposed inter-satellite routing security mechanism effectively mitigated multiple security threats in the space network environment while reduced communication latency caused by sudden link failures, thereby ensured secure and reliable communication within the LEO satellite network.…”
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Survey of FPGA based recurrent neural network accelerator by Chen GAO, Fan ZHANG

“…Recurrent neural network(RNN) has been used wildly used in machine learning field in recent years,especially in dealing with sequential learning tasks compared with other neural network like CNN.However,RNN and its variants,such as LSTM,GRU and other fully connected networks,have high computational and storage complexity,which makes its inference calculation slow and difficult to be applied in products.On the one hand,traditional computing platforms such as CPU are not suitable for large-scale matrix operation of RNN.On the other hand,the shared memory and global memory of hardware acceleration platform GPU make the power consumption of GPU-based RNN accelerator higher.More and more research has been done on the RNN accelerator of the FPGA in recent years because of its parallel computing and low power consumption performance.An overview of the researches on RNN accelerator based on FPGA in recent years is given.The optimization algorithm of software level and the architecture design of hardware level used in these accelerator are summarized and some future research directions are proposed.…”
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Energy-efficient 3D multi-band I/O interface for enhanced mobile memory communication by Ahmed Alzahmi

“…The proposed multi-band I/O (MBI) interface utilizes 3D integration, for two radio frequency band transceivers, and a CMOS driver with resistive feedback for the baseband (BB) transceiver. The proposed design implements a band-selective transformer to enable transmitting three bands, baseband and 2 RF bands (10&30 GHz), simultaneously. …”
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An Efficient GPU-Based Out-of-Core LU Solver of Parallel Higher-Order Method of Moments for Solving Airborne Array Problems by Zhongchao Lin, Yan Chen, Yu Zhang, Xunwang Zhao, Huanhuan Zhang

“…A parallel framework involving MPI and CUDA is adopted to ensure that the procedures run on a hybrid CPU/GPU cluster. An efficient two-level out-of-core scheme is designed to break the bottleneck of both GPU memory and physical memory when solving electrically large and complex problems. …”
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The Comparison of Lately Proposed Harris Hawks Optimization and Jaya Optimization in Solving Directional Overcurrent Relays Coordination Problem by Jiangtao Yu, Chang-Hwan Kim, Sang-Bong Rhee

“…The comparisons show that the robustness and consistency of HHO is relatively better than Jaya, while Jaya provides faster convergence rate with less CPU time and occasionally more competitive objective function value than HHO.…”
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Implementation of Membrane Algorithms on GPU by Xingyi Zhang, Bangju Wang, Zhuanlian Ding, Jin Tang, Juanjuan He

“…Membrane algorithms are a new class of parallel algorithms, which attempt to incorporate some components of membrane computing models for designing efficient optimization algorithms, such as the structure of the models and the way of communication between cells. …”
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Implementasi Algoritma BFCC dan kNN pada Embedded System untuk Deteksi Dini Bronchitis by Septiyo Budi Perkasa, Barlian Henryranu Prasetio, Eko Setiawan, Edita Rosana Widasari, Dahnial Syauqy

“…Hasil pengujian menunjukkan rata-rata waktu komputasi sebesar 4,452 detik dan penggunaan CPU sebesar 26%, serta akurasi kNN sebesar 73% untuk perhitungan jarak Euclidean dengan nilai neighbour = 5.   …”
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