Designing of 2-Stage CPU Scheduler Using Vague Logic by Supriya Raheja, Reena Dhadich, Smita Rajpal

“…In operating system the CPU scheduler is designed in such a way that all the resources are fully utilized. …”
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Accelerating the SM3 hash algorithm with CPU‐FPGA Co‐Designed architecture by Xiaoying Huang, Zhichuan Guo, Mangu Song, Xuewen Zeng

“…However, the performance of implementation on the software architecture is not sufficient for high‐speed applications. This study proposes a CPU‐FPGA co‐designed architecture which offloads the SM3 function on field‐programmable gate array so that high throughput can be achieved. …”
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Position Control of a 3-CPU Spherical Parallel Manipulator by Massimo Callegari, Luca Carbonari, Giacomo Palmieri, Matteo-Claudio Palpacelli, Donatello Tina

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High Performance Computing of Complex Electromagnetic Algorithms Based on GPU/CPU Heterogeneous Platform and Its Applications to EM Scattering and Multilayered Medium Structure by Zhe Song, Xing Mu, Hou-Xing Zhou

“…The fast and accurate numerical analysis for large-scale objects and complex structures is essential to electromagnetic simulation and design. Comparing to the exploration in EM algorithms from mathematical point of view, the computer programming realization is coordinately significant while keeping up with the development of hardware architectures. …”
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An Embedded Cloud Design for Internet-of-Things by Teemu Laukkarinen, Jukka Suhonen, Marko Hännikäinen

“…An embedded cloud design is presented that consists of distributable Process Description Language (PDL), Distributed Middleware (DiMiWa), and an infrastructure. …”
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Genetic analysis of scab disease resistance in common bean (Phaseolus vulgaris) varieties using GWAS and functional genomics approaches by Shadrack Odikara Oriama, Benard W. Kulohoma, Evans Nyaboga, Y. O. Masheti, Reuben Otsyula

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Performance evaluation of designated containerization and virtualization solutions using a synthetic benchmark by Sebastian Tarasiuk, Damian Traczuk, Kacper Szczepaniuk, Patryk Stoń, Jakub Smołka

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Decoupling and Collaboration: An Intelligent Gateway-Based Internet of Things System Architecture for Meat Processing by Jun Liu, Chenggang Zhou, Haoyuan Wei, Jie Pi, Daoying Wang

“…This architecture is centered around an intelligently decoupled gateway design and edge-cloud collaborative intelligent meat inspection. …”
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SpecPCM: A Low-Power PCM-Based In-Memory Computing Accelerator for Full-Stack Mass Spectrometry Analysis by Keming Fan, Ashkan Moradifirouzabadi, Xiangjin Wu, Zheyu Li, Flavio Ponzina, Anton Persson, Eric Pop, Tajana Rosing, Mingu Kang

“…This article introduces SpecPCM, an in-memory computing (IMC) accelerator designed to achieve substantial improvements in energy and delay efficiency for both MS spectral clustering and database (DB) search. …”
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El Consejo Técnico Escolar como dispositivo formativo: la experiencia del ciclo escolar 2022-2023 by Graciela Cordero-Arroyo, María Guadalupe Tinajero Villavicencio, Roxana Patricia León González

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Construction of Personalized Learning Platform Based on Intelligent Algorithm in the Context of Industry Education Integration by Zhifang Qian

“…In order to meet the personalized needs of different students and provide students with a variety of intelligent learning strategies and learning content, this research is aimed at the current lack of intelligent function design in the network teaching platform of colleges and universities. …”
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CUDT: A CUDA Based Decision Tree Algorithm by Win-Tsung Lo, Yue-Shan Chang, Ruey-Kai Sheu, Chun-Chieh Chiu, Shyan-Ming Yuan

“…In the proposed system, CPU is responsible for flow control while the GPU is responsible for computation. …”
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HIGH-PERFORMANCE SIMULATIONS OF POPULATION-GENETIC PROCESSES IN BACTERIAL COMMUNITIES USING THE HAPLOID EVOLUTIONARY CONSTRUCTOR SOFTWARE by Z. S. Mustafin, Yu. G. Matushkin, S. A. Lashin

“…These high-performance versions are to be run on systems with shared and distributed memory, using CPU and/or GPU. Almost linear acceleration has been achieved on clusters and multi-core CPU. …”
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An Efficient GPU-Accelerated Algorithm for Solving Dynamic Response of Fluid-Saturated Porous Media by Wancang Lin, Qinglong Zhou, Xinyi Chen, Wenhao Shi, Jie Ai

“…For a data set with two million degrees of freedom, it takes only about 0.05 s to compute an iterative step and transfer the data to the CPU. The program is designed to calculate either in single or double precision. …”
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Approximate Solutions of Delay Differential Equations with Constant and Variable Coefficients by the Enhanced Multistage Homotopy Perturbation Method by D. Olvera, A. Elías-Zúñiga, L. N. López de Lacalle, C. A. Rodríguez

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Refactoring Android Source Code Smells From Android Applications by Muhammad Fawad, Ghulam Rasool, Muhammad Bilal Riaz

“…This study enhances the Android application development lifecycle by offering developers a feasible solution for optimizing CPU efficiency, reducing memory use, and minimizing battery consumption.…”
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Optimization of Hydraulic Machinery Bladings by Multilevel CFD Techniques by Susanne Thum, Rudolf Schilling

“…The numerical design optimization for complex hydraulic machinery bladings requires a high number of design parameters and the use of a precise CFD solver yielding high computational costs. …”
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FCM Clustering Approach Optimization Using Parallel High-Speed Intel FPGA Technology by Abedalmuhdi Almomany, Amin Jarrah, Anwar Al Assaf

“…Our experimental results (based on several datasets) show that the proposed method makes the FCM execution time more than 186 times faster than the conventional design running on a single-core CPU platform. Also, its processing power reached 89 giga floating points operations per second (GFLOPs).…”
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Multi-Softcore Architecture on FPGA by Mouna Baklouti, Mohamed Abid

“…The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. …”
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RP-Ring: A Heterogeneous Multi-FPGA Accelerator by Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin

“…Our accelerator can achieve two orders of magnitude speedup compared with CPU implementation.…”
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