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Very large scale integration implementation of seizure detection system with on‐chip support vector machine classifier
Published 2022-01-01“…This research work proposes a very large scale integration implementation system for the automatic detection of seizures. …”
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Topology-Aware Bus Routing in Complex Networks of Very-Large-Scale Integration with Nonuniform Track Configurations and Obstacles
Published 2021-01-01“…As one of the most important routing problems in the complex network within a very-large-scale integration (VLSI) circuit, bus routing has become much more challenging when witnessing the advanced technology node enters the deep nanometer era because all bus bits need to be routed with the same routing topology in the context. …”
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An Efficient K-Best MIMO Detector for Large Modulation Constellations
Published 2024-01-01Subjects: Get full text
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An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates
Published 2015-01-01“…At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. …”
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Global Detection of Live Virtual Machine Migration Based on Cellular Neural Networks
Published 2014-01-01“…Compared with the best fit heuristic algorithm, this approach reduces the processing time, and emerging evidence has indicated that this new approach is affordable to parallelism and analog very large scale integration (VLSI) implementation allowing the VM migration detection to be performed better.…”
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A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things
Published 2019-12-01“…The pre-silicon detection methods do not require gold chips, are not affected by process noise, and are suitable for the safe detection of a very large-scale integration. Therefore, more and more researchers are paying attention to the pre-silicon detection method. …”
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Controlling Underwater Robots with Electronic Nervous Systems
Published 2010-01-01“…We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM) neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration) electronic neuron (aVLSI) networks. …”
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