Investigating vertical charge plasma tunnel field effect transistors beyond semiclassical assumptions by Iman Chahardah Cherik, Saeed Mohammadi, Paul K. Hurley, Lida Ansari, Farzan Gity

“…Abstract In this paper, we examine the effects of subband quantization on the efficacy of an L-shaped gate vertical dopingless tunneling field-effect transistor. The proposed architecture leverages an intrinsic tunneling interface that is fully aligned with the gate metal, resulting in enhanced electrostatic control. …”
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DIFFERENT ROLES AND DESIGNS OF HETERO-GATE DIELECTRIC IN SINGLE- AND DOUBLE-GATE TUNNEL FIELD-EFFECT TRANSISTORS by Nguyễn Đăng Chiến, Lưu Thế Vinh, Huỳnh Thị Hồng Thắm, Chun Hsing Shih

“…Hetero-gate dielectric (HGD) engineering not only suppresses the ambipolar current but also enhances the on-current of tunnel field-effect transistors (TFETs). Based on two-dimensional device simulations, we examined the roles and designs of hetero-gate dielectric structure in single- and double-gate TFETs. …”
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A VERY LOW BANDGAP LINE-TUNNEL FIELD EFFECT TRANSISTOR WITH CHANNEL-BURIED OXIDE AND LATERALLY DOPED POCKET by Huu Thai Bui, Chun-Hsing Shih, Dang Chien Nguyen

“… Low bandgap and line tunneling techniques have demonstrated the most effectiveness in enhancing the on-current of tunnel field-effect transistors (TFETs). This study examines the mechanisms and designs of channel-buried oxide and a laterally doped pocket for a very low bandgap line-TFET. …”
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Analytical model and simulation‐based analysis of a work function engineered triple metal tunnel field‐effect transistor device showing excellent device performance by Ria Bose, Jatindra Nath Roy

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Temperature dependence of analogue/RF performance, linearity and harmonic distortion for dual‐material gate‐oxide‐stack double‐gate TFET by Satyendra Kumar

“…Abstract This article presents an investigation report of the effects of temperature variation in the range of 300 to 480 K on electrical performance parameters of conventional dual‐material double‐gate tunnel field effect transistor (DMDG‐TFET) and dual‐material gate‐oxide‐stack double‐gate tunnel field effect transistor (DMGOSDG‐TFET). …”
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Unsupervised Learning in a Ternary SNN Using STDP by Abhinav Gupta, Sneh Saurabh

“…A ternary neuron is implemented using a Dual-Pocket Tunnel Field effect transistor (DP-TFET). The synapse consists of a Magnetic Tunnel Junction (MTJ) with a Heavy Metal (HM) underlayer, allowing for the adjustment of its conductance by directing a current through the HM layer. …”
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Performance Assessment of GaAs Pocket-Doped Dual-Material Gate-Oxide-Stack DG-TFET at Device and Circuit Level by Km. Sucheta Singh, Satyendra Kumar, Saurabh Chaturvedi, Kapil Dev Tyagi, Vaibhav Bhushan Tyagi

“…This study explores the impact of integrating a gallium arsenide (GaAs) pocket at the source and drain in a dual-material gate-oxide-stack double-gate tunnel field-effect transistor (DMGOSDG-TFET). The performance of this DMGOSDG-TFET, employing work-function engineering and gate-oxide-stack techniques, is compared with a GaAs pocket-doped DMGOSDG-TFET. …”
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Implementation and comprehensive investigation of gate engineered Si0.1Ge0.9/GaAs charged plasma based JLTFET for improved analog/ RF performance by Pranita Soni, Aditya Jain, Kaushal Kumar, Lokesh Kumar Soni, Ajay Kumar, Neha Gupta, Amit Kumar Goyal, Rakesh Saroha

“…This study introduces the Variable Length Dual Dielectric Material-Gate Spacer Engineering Heterostructure Junction-Less Tunnel Field-Effect Transistor (VLDD-GSE-HJLTFET), a novel device that integrates advanced bandgap engineering, dual-dielectric gate configuration, and heterostructure design using Si0.1Ge0.9/GaAs layers. …”
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Drive Current Enhancement in TFET by Dual Source Region by Zhi Jiang, Yiqi Zhuang, Cong Li, Ping Wang, Yuqi Liu

“…This paper presents tunneling field-effect transistor (TFET) with dual source regions. …”
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A New Type of Tri-Input TFET with T-Shaped Channel Structure Exhibiting Three-Input Majority Logic Behavior by Ye Hao, Jiang Zhidi, Hu Jianping

“…In this paper, we propose a new type of tri-input tunneling field-effect transistor (Ti-TFET) that can compactly realize the “Majority-Not” logic function with a single transistor. …”
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Study on Single Event Upset and Mitigation Technique in JLTFET-Based 6T SRAM Cell by Aishwarya K, Lakshmi B

“…The effect of single event transient (SET) on 6T SRAM cell employing a 20 nm silicon-based junctionless tunneling field effect transistor (JLTFET) is explored for the first time. …”
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