100 nm AlSb/InAs HEMT for Ultra-Low-Power Consumption, Low-Noise Applications by Cyrille Gardès, Sonia Bagumako, Ludovic Desplanque, Nicolas Wichmann, Sylvain Bollaert, François Danneville, Xavier Wallart, Yannick Roelens

“…We report on high frequency (HF) and noise performances of AlSb/InAs high electron mobility transistor (HEMT) with 100 nm gate length at room temperature in low-power regime. …”
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Pressure-dependent current transport in vertical BP/MoS2 heterostructures by Ofelia Durante, Sebastiano De Stefano, Adolfo Mazzotti, Loredana Viscardi, Filippo Giubileo, Osamah Kharsah, Leon Daniel, Stephan Sleziona, Marika Schleberger, Antonio Di Bartolomeo

“…The results of this work highlight the potential of BP/MoS2 heterostructures for applications in low-power electronics, high-performance transistors, and sensitive pressure sensors.…”
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Vertical Silicon Nanowire Platform for Low Power Electronics and Clean Energy Applications by D.-L. Kwong, X. Li, Y. Sun, G. Ramanathan, Z. X. Chen, S. M. Wong, Y. Li, N. S. Shen, K. Buddharaju, Y. H. Yu, S. J. Lee, N. Singh, G. Q. Lo

“…Under electronics domain, besides having ultimate scaling potential, the vertical wire offers (1) CMOS circuits with much smaller foot print as compared to planar transistor at the same technology node, (2) a natural platform for tunneling FETs, and (3) a route to fabricate stacked nonvolatile memory cells. …”
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Implementation and comprehensive investigation of gate engineered Si0.1Ge0.9/GaAs charged plasma based JLTFET for improved analog/ RF performance by Pranita Soni, Aditya Jain, Kaushal Kumar, Lokesh Kumar Soni, Ajay Kumar, Neha Gupta, Amit Kumar Goyal, Rakesh Saroha

“…This study introduces the Variable Length Dual Dielectric Material-Gate Spacer Engineering Heterostructure Junction-Less Tunnel Field-Effect Transistor (VLDD-GSE-HJLTFET), a novel device that integrates advanced bandgap engineering, dual-dielectric gate configuration, and heterostructure design using Si0.1Ge0.9/GaAs layers. …”
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Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology by Alfonso R. Cabrera-Galicia, Arun Ashok, Patrick Vliex, Andre Kruth, Andre Zambanini, Stefan van Waasen

“…Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. …”
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Variation of the Side Chain Branch Position Leads to Vastly Improved Molecular Weight and OPV Performance in 4,8-dialkoxybenzo[1,2-b:4,5-b′]dithiophene/2,1,3-benzothiadiazole Copol... by Robert C. Coffin, Christopher M. MacNeill, Eric D. Peterson, Jeremy W. Ward, Jack W. Owen, Claire A. McLellan, Gregory M. Smith, Ronald E. Noftle, Oana D. Jurchescu, David L. Carroll

“…The hole mobility as determined by thin film transistor (TFT) measurements is improved from ~1×10−6 cm2/Vs for P1 and P2 to 7×10−4 cm2/Vs for P3, while solar cell power conversion efficiency in increased to 2.91% for P3 relative to 0.31% and 0.19% for P1 and P2, respectively.…”
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Impact of gate metals/high-K materials and lateral scaling on the performance of AlN/GaN/AlGaN-MOSHEMT on SiC wafer for future microwave power amplifiers in RADAR & communicati... by Gauri Deshpande, J. Ajayan, Sandip Bhattacharya, B. Mounika, Amit Krishna Dwivedi, D. Nirmal

“…An innovative GaN-channel MOSHEMT (Metal-oxide-semiconductor-high-electron-mobility-transistor) featuring AlGaN aback barrier and AlN barrier is reported. …”
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Random resistive memory-based deep extreme point learning machine for unified visual processing by Shaocong Wang, Yizhao Gao, Yi Li, Woyu Zhang, Yifei Yu, Bo Wang, Ning Lin, Hegan Chen, Yue Zhang, Yang Jiang, Dingchen Wang, Jia Chen, Peng Dai, Hao Jiang, Peng Lin, Xumeng Zhang, Xiaojuan Qi, Xiaoxin Xu, Hayden So, Zhongrui Wang, Dashan Shang, Qi Liu, Kwang-Ting Cheng, Ming Liu

“…Moreover, conventional digital hardware is constrained by von Neumann bottleneck and the physical limit of transistor scaling. The computational demands of training ever-growing models further exacerbate these challenges. …”
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A High Performance Adaptive Digital LDO Regulator With Dithering and Dynamic Frequency Scaling for IoT Applications by Muhammad Asif, Imran Ali, Danial Khan, Muhammad Riaz Ur Rehman, Qurat- Ul-Ain, Muhammad Basim, Young Gun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee

“…The multi-loop architecture with hill climbing reduces the total bi-directional shift registers length which results in the reduced leakage current in the transistor-switch-array (TSA), and improves the recovery time and output DC voltage accuracy. …”
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Basic Characteristics of Ionic Liquid-Gated Graphene FET Sensors for Nitrogen Cycle Monitoring in Agricultural Soil by Naoki Shiraishi, Jian Lu, Fatin Bazilah Fauzi, Ryo Imaizumi, Toyohiro Tsukahara, Satoshi Mogari, Shosuke Iida, Yusuke Matsukura, Satoshi Teramoto, Keisuke Yokoi, Izumi Ichinose, Mutsumi Kimura

“…To achieve this, we developed ionic liquid-gated graphene field-effect transistor (FET) sensors to measure N₂O concentrations in agricultural soil. …”
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Characterization and simulation of AlGaN barrier structure effects in normally-off recessed gate AlGaN/GaN MISHEMTs by An-Chen Liu, Hsin-Chu Chen, Po-Tsung Tu, Yan-Lin Chen, Yan-Chieh Chen, Po-Chun Yeh, Chih-I Wu, Shu-Tong Chang, Tsung-Sheng Kao, Hao-Chung Kuo

“…The objective of this study is to optimize the trade-off between threshold voltage (V _TH ) and maximum drain current (I _D,max ) in recessed gate AlGaN/GaN metal insulator semiconductor high electron mobility transistor (MISHEMT) using atomic layer etching (ALE) technology, with technical computer-aided design (TCAD) simulations assisting in the analysis of the underlying mechanisms to demonstrate the high performance and reliability of GaN-based power application. …”
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A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product by Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta

“…Based on the proposed structure, traditional C2MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C2MOS based flip-flop designs mC2MOSff1 and mC2MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC2MOSff1. …”
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Formation and Device Application of Ge Nanowire Heterostructures via Rapid Thermal Annealing by Jianshi Tang, Chiu-Yen Wang, Faxian Xiu, Yi Zhou, Lih-Juann Chen, Kang L. Wang

“…Our Ge nanowire transistors have shown a high-performance p-type behavior with a high on/off ratio of 105 and a field-effect hole mobility of 210 cm2/Vs, which showed a significant improvement compared with that from unreacted Ge nanowire transistors.…”
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An AMOLED AC-Biased Pixel Design Compensating the Threshold Voltage and I-R Drop by Ching-Lin Fan, Hui-Lung Lai, Yan-Wei Liu

“…We propose a novel pixel design and an AC bias driving method for active-matrix organic light-emitting diode (AM-OLED) displays using low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). The proposed threshold voltage and I-R drop compensation circuit, which comprised three transistors and one capacitor, have been verified to supply uniform output current by simulation work using the Automatic Integrated Circuit Modeling Simulation Program with Integrated Circuit Emphasis (AIM-SPICE) simulator. …”
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A Current-mode Logarithmic Function Circuit by Muhammad Taher Abuelma'atti, Osama Oglah Faris

“…The circuit uses bipolar transistors and resistors and is suitable for integration. …”
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Measurements and Analytical Computer-Based Study of CMOS Inverters and Schmitt Triggers by Umesh Kumar

“…Modified CMOS inverters with three and four transistors have been made. Two varieties of CMOS Schmitt Triggers have been considered. …”
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A New Junction Parameters Determination Using the Double Exponential Model by S. Dib, A. Khoury, F. PéLanchon, P. Mialhe

“…An experimental test considers the emitter-base junction of bipolar transistors.…”
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CMOS Realization of All-Positive Pinched Hysteresis Loops by B. J. Maundy, A. S. Elwakil, C. Psychalinos

“…These circuits employ two NMOS transistors, one of which operates in its triode region, in addition to two first-order filter sections. …”
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Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach by Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh

“…Impact of strain of sub-3 nm gate-all-around (GAA) CMOS transistors on the circuit performance is evaluated using a neural compact model. …”
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Analog Low-Voltage Current-Mode Implementation of Digital Logic Gates by Muhammad Taher Abuelma'atti

“…By expanding the logic functions in power series expressions, and using summers and multipliers, realization of the basic logic functions is simplified. Since no transistors are working in saturation, the problem of fan-out is alleviated. …”
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