A Taxonomy of Reconfigurable Single-/Multiprocessor Systems-on-Chip by Diana Göhringer, Thomas Perschke, Michael Hübner, Jürgen Becker

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Challenges to adopting adiabatic circuits for systems‐on‐a‐chip by Krishnan S. Rengarajan, Saroj Mondal, Ravindra Kapre

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Ultrahigh-Performance Radio Frequency System-on-Chip Implementation of a Kalman Filter-Based High-Precision Time and Frequency Synchronization for Networked Integrated Sensing and Communication Systems by Roghayeh Ghasemi, Patrick Fenske, Tobias Koegel, Markus Hehn, Ingrid Ullmann, Martin Vossiek

“…In this article, a novel real-time wireless time and frequency synchronization scheme is developed and fully implemented on a high-end radio frequency system-on-chip field-programmable gate array (FPGA) platform. …”
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REAL-TIME KERNEL FUNCTION SYNTHESIS FOR SOFTWAREDEFINED RADIO AND PHASE-FREQUENCY MEASURING DIGITAL SYSTEMS by I. E. Tarasov, D. S. Potekhin

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All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops by Lanhua Xia, Jifei Tang

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Real-Time Monitoring Method and Circuit Based on Built-In Reliability Prediction by Wenke Ren, Yanning Chen, Xiaoming Li, Xinjie Zhou, Baichen Song, Tianci Chang

“…This paper proposes three system-on-chip reliability failure prediction unit circuits: the time-dependent dielectric breakdown prediction circuit, the negative bias temperature instability prediction circuit, and the hot carrier injection prediction circuit. …”
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Performance survey of classic and Optic network‐on‐chip by Moez Balti, Abderrazak JEMAI

“…Abstract A system on chip is composed of a large number of intellectual property (IP) blocks on the same silicon. …”
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Toward the Implementation of an ASIC-Like System on FPGA for Real-Time Video Processing with Power Reduction by Lilia Kechiche, Lamjed Touil, Bouraoui Ouni

“…Driven by the importance of energy consumption in system-on-chip design as an evaluation factor, this paper presents a design methodology at the system level to optimize power consumption on ARM-based architecture for real-time video processing. …”
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Memory Map: A Multiprocessor Cache Simulator by Shaily Mittal, Nitin

“…Nowadays, Multiprocessor System-on-Chip (MPSoC) architectures are mainly focused on by manufacturers to provide increased concurrency, instead of increased clock speed, for embedded systems. …”
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A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands by Anish S. Kumar, M. Pawan Kumar, Srinivasan Murali, V. Kamakoti, Luca Benini, Giovanni De Micheli

“…Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.…”
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Networks on Chips: Structure and Design Methodologies by Wen-Chung Tsai, Ying-Cherng Lan, Yu-Hen Hu, Sao-Jie Chen

“…The next generation of multiprocessor system on chip (MPSoC) and chip multiprocessors (CMPs) will contain hundreds or thousands of cores. …”
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Very large scale integration implementation of seizure detection system with on‐chip support vector machine classifier by Shalini Shanmugam, Selvathi Dharmar

“…Efficient results were produced compared with the existing system on chip (SoC) and FPGA seizure detection systems.…”
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On broadband, linear-phase, flat group delay, all-pole, low-pass filters for high-speed, data communication by Mihai Sanduleanu, Dan Cracan

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High level modeling of Dynamic Reconfigurable FPGAs by Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser

“…As System-on-Chip (SoC) based embedded systems have become a defacto industry standard, their overall design complexity has increased exponentially in recent years, necessitating the introduction of new seamless methodologies and tools to handle the SoC codesign aspects. …”
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Reliability Analysis of Baremetal and FreeRTOS Applications on Microchip PolarFire SoC RISC-V Multiprocessors Using High-Energy Protons by Andre M. P. Mattos, Douglas A. Santos, Luigi Dilillo

“…In this context, we propose the analysis and characterization of software applications’ reliability on a novel RISC-V-based processing system: Microchip’s PolarFire System-on-Chip (SoC). For that, we introduce reliability benchmarks using baremetal and FreeRTOS implementations and perform an experimental evaluation using high-energy protons, reporting Single-Event Effects (SEE) cross sections and the impact of Total Ionizing Dose (TID). …”
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A Hardware Accelerator for the Inference of a Convolutional Neural network by Edwin González, Walter D. Villamizar Luna, Carlos Augusto Fajardo Ariza

“…The design was implemented in the Digilent Arty Z7-20 development board, which is based on System on Chip (SoC) Zynq-7000 of Xilinx. Our implementation achieved a  of accuracy for the MNIST database using only 12-bits fixed-point format. …”
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Improving the Performance of Whale Optimization Algorithm through OpenCL-Based FPGA Accelerator by Qiangqiang Jiang, Yuanjun Guo, Zhile Yang, Zheng Wang, Dongsheng Yang, Xianyu Zhou

“…In this paper, field programmable gate array (FPGA) is used as an accelerator, of which the high-level synthesis utilizes open computing language (OpenCL) as a general programming paradigm for heterogeneous System-on-Chip. With above platform, a novel parallel framework of WOA named PWOA is presented. …”
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A Review on Frequency Compensation and Transient Enhancement Schemes of Flipped Voltage Follower LDO Regulators for SoC Applications by P. Manikandan, B. Bindu

“…The output capacitor-less LDOs are attractive for system-on-chip (SoC) applications, however the removal of the external capacitor degrades its stability and transient responses. …”
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Analysis of Effective Broodstock Management and Breeding of Patin Siam (Pangasius hypophthalmus) in BBAT Jambi by Mimid A. Hamid, Wahyu B. W, Rangga W, Reni A. Lubis, Atomu Furusawa

“…Semua betina ditandai dengan menggunakan PIT tag system (micro chip).  Perkembangan kematangan gonad dimonitor tiap bulan. …”
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Multilevel Simulation of Heterogeneous Reconfigurable Platforms by Damien Picard, Loic Lagadec

“…This paper presents a general system-level simulation and testing methodology for reconfigurable System-on-Chips, starting from behavioral specifications of system activities to multilevel simulations of accelerated tasks running on the reconfigurable circuit. …”
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