Showing 1 - 10 results of 10 for search '"phase-locked loop"', query time: 0.04s Refine Results
  1. 1
    Mitigation of Harmonics and Unbalanced Voltage Disturbance Compensation by MSVPWM Based- DVR in the Distribution Net

    Mitigation of Harmonics and Unbalanced Voltage Disturbance Compensation by MSVPWM Based- DVR in the Distribution Net by Haider Muhamad Husen

    Published 2021-07-01
    Subjects: “…Phase-Locked Loop, MDCC, DVR, Space-Vector Control, Compensation Strategy, THD%.…”
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  2. 2
    Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers

    Insights Into Architectural Spurs in High-Performance Fractional-<italic>N</italic> Frequency Synthesizers by Michael Peter Kennedy, Xu Lu, Xu Wang

    Published 2024-01-01
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  3. 3
    A Second Harmonic Current Suppression Strategy Based on a Digital Band-Stop Filter With Center Frequency Tracking Grid Frequency

    A Second Harmonic Current Suppression Strategy Based on a Digital Band-Stop Filter With Center Frequency Tracking Grid Frequency by Jun-Hyeong Kwon, Guangxu Zhou, Chun-Sung Kim, Sung-Jun Park, Yipei Wang

    Published 2025-01-01
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  4. 4
    Features of pressure control in pipelines of spacecraft propulsion systems

    Features of pressure control in pipelines of spacecraft propulsion systems by I. V. Platov, Е. V. Leun, A. I. Сheredov, Yu. N. Mishin

    Published 2019-10-01
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  5. 5
    On construction of laser acousto-optical heterodyne interferometers with push-pull measurement of product motions

    On construction of laser acousto-optical heterodyne interferometers with push-pull measurement of product motions by E. V. Leun

    Published 2020-06-01
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  6. 6
    A&#x2013;102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL

    A&#x2013;102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL by Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers

    Published 2024-01-01
    Subjects: “…All-digital phase-locked loop (ADPLL)…”
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  7. 7
    Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques

    Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques by Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski

    Published 2024-01-01
    Subjects: “…All-digital phase-locked loop (ADPLL)…”
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  8. 8
    Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation

    Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation by Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski

    Published 2024-01-01
    Subjects: “…All-digital phase-locked loop (ADPLL)…”
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  9. 9
    Impact of Frequency Heterogeneity on Mutually Synchronized Spatially Distributed 24 GHz PLLs

    Impact of Frequency Heterogeneity on Mutually Synchronized Spatially Distributed 24 GHz PLLs by Christian Hoyer, Jens Wagner, Frank Ellinger

    Published 2024-01-01
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  10. 10
    All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops

    All‐digital built‐in self‐test scheme for charge‐pump phase‐locked loops by Lanhua Xia, Jifei Tang

    Published 2021-01-01
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