Showing 1 - 4 results of 4 for search '"parallel-prefix adder"', query time: 0.07s Refine Results
  1. 1
    Design of a low-delay 4-bit parallel prefix adder using QCA technology

    Design of a low-delay 4-bit parallel prefix adder using QCA technology by Tushar Niranjan, Anirban Nayak, Sreehari Veeramachaneni, Syed Ershad Ahmed

    Published 2025-07-01
    Subjects: “…Parallel prefix adder…”
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  2. 2
    Comparative analysis of adders hardware implementation on FPGA

    Comparative analysis of adders hardware implementation on FPGA by Nikolay Ivanovich Chervyakov, Pavel Alekseyevich Lyakhov, Maria Vasilevna Valueva, O. V. Krivolapova

    Published 2022-09-01
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  3. 3
    HIGH-SPEED MULTIPLIER DESIGN BASED ON AN OPTIMIZED PARALLEL PREFIX TREE ARCHITECTURE

    HIGH-SPEED MULTIPLIER DESIGN BASED ON AN OPTIMIZED PARALLEL PREFIX TREE ARCHITECTURE by D. V. N. Bharathi, Y Varthamanan

    Published 2025-06-01
    Subjects: “…high speed multiplier, parallel prefix tree, multiplier optimization, digital signal processing, parallel prefix adder, low power architecture.…”
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  4. 4
    Towards Fast Implementation of Complex RNS Components on FPGAs

    Towards Fast Implementation of Complex RNS Components on FPGAs by Sabbagh Molahosseini Amir, Alsadat Emrani Azadeh

    Published 2022-09-01
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