Analysis and Design of FeFET Synapse With Stacked-Nanosheet Architecture Considering Cycle-to-Cycle Variations for Neuromorphic Applications by Heng Li Lin, Pin Su

Subjects: “…Stacked nanosheet…”
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SRAM and Mixed-Signal Logic With Noise Immunity in 3-nm Nano-Sheet Technology by Rajiv V. Joshi, J. Frougier, Alberto Cestero, Crystal Castellanos, Sudipto Chakraborty, Carl Radens, M. Silvestre, S. Lucarini, I. Ahsan, E. Leobandung

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Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering by Xuexiang Zhang, Qingkun Li, Lei Cao, Qingzhu Zhang, Renjie Jiang, Peng Wang, Jiaxin Yao, Huaxiang Yin

Subjects: “…Gate-all-around nanosheet transistor (GAA NSFET)…”
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