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  1. 1
    Algorithms for partitioning logical circuits into subcircuits

    Algorithms for partitioning logical circuits into subcircuits by N. A. Kirienko

    Published 2020-09-01
    Subjects: “…logical circuit…”
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  2. 2
    Pinched hysteresis loops in non‐linear resonators

    Pinched hysteresis loops in non‐linear resonators by Ahmed S. Elwakil, Mohammed E. Fouda, Sohaib Majzoub, Ahmed G. Radwan

    Published 2021-03-01
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  3. 3
    Challenges to adopting adiabatic circuits for systems‐on‐a‐chip

    Challenges to adopting adiabatic circuits for systems‐on‐a‐chip by Krishnan S. Rengarajan, Saroj Mondal, Ravindra Kapre

    Published 2021-09-01
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  4. 4
    Energy-Efficient Discrete Cosine Transform Architecture Using Reversible Logic for IoT-Enabled Consumer Electronics

    Energy-Efficient Discrete Cosine Transform Architecture Using Reversible Logic for IoT-Enabled Consumer Electronics by Muhammad Awais, Wilayat Khan, Tallha Akram, Yunyoung Nam

    Published 2025-01-01
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  5. 5
    Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices

    Binary decision diagram‐based synthesis technique for improved mapping of Boolean functions inside memristive crossbar‐slices by Anindita Chakraborty, Vivek Maurya, Sneha Prasad, Suryansh Gupta, Rajat Subhra Chakraborty, Hafizur Rahaman

    Published 2021-03-01
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  6. 6
    Noise‐based logic locking scheme against signal probability skew analysis

    Noise‐based logic locking scheme against signal probability skew analysis by Ahmad Rezaei, Ali Mahani

    Published 2021-07-01
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  7. 7
    TVD‐PB logic circuit based on camouflaging circuit for IoT security

    TVD‐PB logic circuit based on camouflaging circuit for IoT security by Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu

    Published 2022-01-01
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  8. 8
    Comprehensive survey of ternary full adders: Statistics, corrections, and assessments

    Comprehensive survey of ternary full adders: Statistics, corrections, and assessments by Sarina Nemati, Mostafa Haghi Kashani, Reza Faghih Mirzaee

    Published 2023-05-01
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  9. 9
    A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage

    A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage by Jérôme K. Folla, Maria L. Crespo, Evariste T. Wembe, Mohammad A. S. Bhuiyan, Andres Cicuttin, Bernard Z. Essimbi, Mamun B. I. Reaz

    Published 2021-01-01
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  10. 10
    Fundamentals of Digital Logic with Verilog Design /

    Fundamentals of Digital Logic with Verilog Design / by Brown, Stephen D.

    Published 2014
    Subjects: “…Logic circuits Design and construction Data processing. 1689…”
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