Si Substrate Backside—An Emerging Physical Attack Surface for Secure ICs in Flip Chip Packaging by Makoto Nagata, Takuji Miki

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DHRCA: A Design of Security Architecture Based on Dynamic Heterogeneous Redundant for System on Wafer by Bo Mei, Zhengbin Zhu, Peijie Li, Bo Zhao

“…However, traditional HTs protection techniques cannot guarantee complete protection against HTs, which poses a great challenge to the hardware security of SoW. In this paper, we propose a computing architecture based on endogenous security theory—dynamic heterogeneous redundant computing architecture (DHRCA) that can tolerate and detect HTs at runtime. …”
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MARPUF: physical unclonable function with improved machine learning attack resistance by Somanath Tripathy, Vikash Kumar Rai, Jimson Mathew

“…Although PUF is very useful in the area of hardware security, it is vulnerable to machine learning modelling attacks (ML‐MA) by modelling the challenge‐response pairs (CRPs) behaviour. …”
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Analysis and Improvement of a Robust User Authentication Framework for Ubiquitous Sensor Networks by Ling Chi, Liang Hu, Hongtu Li, Jianfeng Chu

“…Another is using the Hardware Security Module. After a simple analysis, we have proved that the improved scheme can resist the collusion attack.…”
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A machine-learning-based hardware-Trojan detection approach for chips in the Internet of Things by Chen Dong, Jinghui Chen, Wenzhong Guo, Jian Zou

“…With the development of the Internet of Things, smart devices are widely used. Hardware security is one key issue in the security of the Internet of Things. …”
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Framework to analyze and exploit the smart home IoT firmware by Keshav Kaushik, Akashdeep Bhardwaj, Susheela Dahiya

“…Since operating system (OS) and hardware security have improved recently, researchers and hackers now seek vulnerabilities in other areas, such as firmware. …”
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TVD‐PB logic circuit based on camouflaging circuit for IoT security by Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu

“…A logic camouflaging circuit is proposed that uses a balanced power consumption and threshold voltage‐defined technique to provide an antiphysical attack scheme to protect the hardware security for IoT devices. The proposed circuit uses a symmetric differential pull‐down network in implementing the different logic functions through the threshold voltage reconfiguration circuit. …”
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