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1
Multi‐precision binary multiplier architecture for multi‐precision floating‐point multiplication
Published 2021-08-01Subjects: Get full text
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2
FPGA‐based implementation of floating point processing element for the design of efficient FIR filters
Published 2021-07-01Subjects: Get full text
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3
Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing
Published 2021-07-01Subjects: Get full text
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