Extending locked range of digital phase-locked loop by prediction estimation of states by ZHAO Yi-bo1, LUO Xiao-shu2, ZHANG Dao-yang3, FENG Jiu-chao1

Subjects: “…digital phase-locked loop…”
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A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL by Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers

Subjects: “…All-digital phase-locked loop (ADPLL)…”
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Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques by Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski

Subjects: “…All-digital phase-locked loop (ADPLL)…”
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Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation by Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski

Subjects: “…All-digital phase-locked loop (ADPLL)…”
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Parameters design and performance analysis of the timing recovery loop based on Gardner timing detector by Yong-ming FU, Jiang ZHU, Ying-jue JU

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