C3-VQA: Cryogenic Counter-Based Coprocessor for Variational Quantum Algorithms by Yosuke Ueno, Satoshi Imamura, Yuna Tomida, Teruo Tanimoto, Masamitsu Tanaka, Yutaka Tabuchi, Koji Inoue, Hiroshi Nakamura

“…Based on the workload analysis and domain-specific system design focused on variational quantum algorithms (VQAs), we propose the cryogenic counter-based coprocessor for VQAs (C3-VQA) to enhance the design scalability of cryogenic quantum computers under the thermal constraint. …”
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Adaptable Security in Wireless Sensor Networks by Using Reconfigurable ECC Hardware Coprocessors by J. Portilla, A. Otero, E. de la Torre, T. Riesgo, O. Stecklina, S. Peter, P. Langendörfer

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Homeland security video surveillance system utilising the internet of video things for smart cities by Yasser Ismail, Mohamed Hammad, Mahmoud Darwich, Wael Elmedany

Subjects: “…coprocessors…”
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Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications by Pablo F. Ramos, Vanessa C. Vargas, Nacer-Eddine Zergainoh, Raoul Velazco

“…Additionally, the E16G301 is the coprocessor for parallel processing of the Parallella platform, which was considered by NASA researchers for onboard health management of the DragonEye UAS. …”
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Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units by João Bispo, Nuno Paulino, João M. P. Cardoso, João Canas Ferreira

“…The ability to map instructions running in a microprocessor to a reconfigurable processing unit (RPU), acting as a coprocessor, enables the runtime acceleration of applications and ensures code and possibly performance portability. …”
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Probing Quantum Telecloning on Superconducting Quantum Processors by Elijah Pelofske, Andreas Bartschi, Stephan Eidenbenz, Bryan Garcia, Boris Kiefer

“…Quantum telecloning can be implemented as a circuit on quantum computers using a classical coprocessor to compute classical feedforward instructions using if statements based on the results of a midcircuit Bell measurement in real time. …”
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A Domain-Specific Architecture for Elementary Function Evaluation by Anuroop Sharma, Christopher Kumar Anand

“…We propose a Domain-Specific Architecture for elementary function computation to improve throughput while reducing power consumption as a model for more general applications: support fine-grained parallelism by eliminating branches, and eliminate the duplication required by coprocessors by decomposing computation into instructions which fit existing pipelined execution models and standard register files. …”
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Mapping Iterative Medical Imaging Algorithm on Cell Accelerator by Meilian Xu, Parimala Thulasiraman

“…The Cell BE consists of one powerPC processor element (PPE) and eight SIMD coprocessors known as synergetic processor elements (SPEs). …”
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