Showing 1 - 1 results of 1 for search '"circuit performance"', query time: 0.03s Refine Results
  1. 1
    Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach

    Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach by Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh

    Published 2024-01-01
    Subjects:
    Get full text
    Article
    Save to List
    Saved in:

Search Tools: