Showing 1 - 2 results of 2 for search '"Verilog HDL"', query time: 0.02s Refine Results
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    Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications

    Design and evaluation of clock-gating-based approximate multiplier for error-tolerant applications by Venkata Sudhakar Chowdam, Suresh Babu Potladurty, Prasad Reddy karipireddy

    Published 2025-04-01
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  2. 2
    High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA

    High-Performance Digital Devices Design by the ASMD-FSMD Technique for Implementation in FPGA by Valery Salauyou, Adam Klimowicz, Tomasz Grzes

    Published 2025-01-01
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