VLSI design of symmetric two-dimensional finite impulse response filter architecture using approximate circuits and parallel Processing by Venkata Krishna Odugu, Gade Harish Babu, Janardhana Rao B, C Venkata Narasimhulu

“…This study presents an innovative filter architecture for a Two-Dimensional (2-D) FIR filter and illustrates its implementation in VLSI design through symmetric processing, parallelism, and approximate computing principles. …”
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Center of Largest Area Defuzzifier Vnit VLSI Architecture by Asim Majeed Murshid, Ahmed Chalak Shakir, Sarmed Nihad Mohammed

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Center of Sums based Defuzzifier Unit VLSI Architecture by Asim Majeed Murshid

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A single-camera gaze tracking system under natural light by Feng Xiao, Dandan Zheng, Kejie Huang, Yue Qiu, Haibin Shen

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Analysis and Design of a Low-Voltage High-Precision Switched-Capacitor Delta–Sigma Modulator by Weiqiang Chen, Lingxin Meng, Menglian Zhao, Zhichao Tan

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A High-Efficiency Piezoelectric Energy Harvesting and Management Circuit Based on Full-Bridge Rectification by Shuhan Liu, Suhao Chen, Wei Gao, Jiabin Zhang, Dacheng Xu, Fang Chen, Zhenghao Lu, Xiaopeng Yu

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Non-Profiled Partial Nibble Recovery on Power Attack Resilient Adiabatic PRESENT Block Cipher Through AI Vulnerability Assessment by Anjana Jyothi Banu, A. A.

“…Circuit-level countermeasures aim to enhance security against SCA at the most fundamental abstraction of VLSI design. Artificial Intelligence (AI) techniques, by eliminating the need for prior knowledge of cryptographic algorithms, have emerged as powerful tools for executing effective SCAs on secure implementations. …”
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Design and Implementation of a Hybrid SET-CMOS Based Sequential Circuits by Anindya Jana, Rajatsuvra Halder, J.K. Sing, Subir Kumar Sarkar

“…Single Electron Transistor is a hot cake in the present research area of VLSI design and Microelectron-ics technology. It operates through one-by-one tunneling of electrons through the channel, utilizing the Coulomb blockade Phenomenon. …”
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Very-Large-Scale Integration (VLSI) Implementation and Performance Comparison of Multiplier Topologies for Fixed- and Floating-Point Numbers by Abimael Jiménez, Antonio Muñoz

“…In this work, a very-large-scale integration (VLSI) design and delay/area performance comparison of array, Wallace tree, and radix-4 Booth multipliers was performed. …”
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Minimization of binary decision diagrams for systems of completely defined Boolean functions using Shannon expansions and algebraic representations of cofactors by P. N. Bibilo, V. I. Romanov

“…In the systems of digital VLSI design (Very Large Integrated Circuits), the BDD (Binary Decision Diagram) is used for VLSI verification, as well as for technologically independent optimization as the first stage in the synthesis of logic circuits in various technological bases. …”
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Mechanical Behavior of Silica Fume Concrete Filled with Steel Tubular Composite Column by Maganti Sandeep Kauthsa Sharma, S. Umadevi, Yerra Sai Sampath, K. Vasugi, K. J. N. Sai Nitesh, V. Swamy Nadh, L. Natrayan

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HIGH-SPEED MULTIPLIER DESIGN BASED ON AN OPTIMIZED PARALLEL PREFIX TREE ARCHITECTURE by D. V. N. Bharathi, Y Varthamanan

“…In modern Very-Large-Scale Integration (VLSI) design, optimizing the power, area, and speed trade-offs is critical to achieving high performance. …”
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A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique by Xiaohui Fan, Yangbo Wu, Hengfeng Dong, Jianping Hu

“…Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. …”
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An Area-Efficient TMR Architecture Inspired From Fast FIR Algorithm for Fault Tolerance by M. Deepa, P. Augusta Sophy Beulet

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High-Speed CMOS Synchronous Binary Counter With Constant Counting Rate by Sungho Kim, Jeongmin Kim, In-Cheol Park

“…In VLSI design, the counter stands as one of the most fundamental and widely utilized components. …”
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Enhanced Digital Acoustic Perception in Hearing Aid Device Using Reconfigurable Filter Bank Structure: A Systematic Review with Recommendation by Rekha Karuppaiah, Umadevi Seerengasamy, Nagajayanthi Boobalakrishnan

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Algorithm for Mining Maximal Balanced Bicliques Using Formal Concept Analysis by Ilkhomjon Sadriddinov, Sony Peng, Sophort Siet, Dae-Young Kim, Doo-Soon Park, Gangman Yi

“…In bipartite graph analysis, the detection of maximal balanced bicliques (MBB) is an important problem with numerous applications, including VLSI design, protein interactions, and social networks. …”
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Employing a Mixture of Rayleigh and Inverse Gaussian Distributions as SAR Clutter Texture Model in MAP Estimation for Efficient Speckle Suppression by Dheeren Ku Mahapatra, Saurav Gupta, Biswajit Jena, Ravi Prakash Dwivedi

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A Physical Charge-Based Analytical Threshold Voltage Model for Cryogenic CMOS Design by Hao Su, Yiyuan Cai, Shenghua Zhou, Guangchong Hu, Yu He, Yunfeng Xie, Yuhuan Lin, Chunhui Li, Tianqi Zhao, Jun Lan, Wenhui Wang, Wenxin Li, Feichi Zhou, Xiaoguang Liu, Longyang Lin, Yida Li, Hongyu Yu, Kai Chen

“…The model retains standard threshold voltage definition by various charges across the MOSFET capacitor while being analytical in its form, therefore, suitable for cryogenic CMOS VLSI design. Consequently, a model covering each and all above characteristics is proposed for the first time. …”
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Electrical Modelling of Multilevel On-Chip Interconnections for High-Speed Integrated Circuits by K. Z. Dimopoulos, J. N. Avaritsiotis, S. J. White

“…It can be used by the VLSI designer to analyze on-chip interconnections with linear, as well as nonlinear/time varying terminators and to simulate the pulse propagation characteristics in high-speed integrated circuits. …”
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