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VLSI design of an irregular LDPC decoder in DTMB
Published 2007-01-01Subjects: Get full text
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VLSI architecture design of motion compensation for MPEG-4
Published 2005-01-01“…The experimental results show that the VLSI processor designed can perform correct logic functions and can achieve a real-time coding for MPEG-4 Core Profile and Level 2.…”
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PAGR: Accelerating Global Routing for VLSI Design Flow
Published 2025-01-01Subjects: Get full text
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VLSI Structure for an All Digital Receiver for CDMA PABX Handset
Published 1995-01-01Get full text
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A New Statistical Method for Maximum Power Estimation in CMOS VLSI Circuits
Published 2000-01-01Subjects: Get full text
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VLSI Architectures for Sliding-Window-Based Space-Time Turbo Trellis Code Decoders
Published 2012-01-01“…The VLSI implementation of SISO-MAP decoders used for traditional iterative turbo coding has been investigated in the literature. …”
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VLSI implementation of AES algorithm against differential power attack and differential fault attack
Published 2010-01-01Subjects: Get full text
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A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique
Published 2013-01-01Get full text
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An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates
Published 2015-01-01“…At present, the design of a competent system in Very Large Scale Integration (VLSI) technology requires these VLSI parameters to be finely defined. …”
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Multiplierless discrete Fourier transform based on moments
Published 2009-01-01Subjects: Get full text
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