FPGA‐based implementation of floating point processing element for the design of efficient FIR filters by Tintu Mary John, Shanty Chacko

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Obfuscation of combination circuits of digital devices from unauthorized access by L. A. Zolotorevich

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Canonization of graphs during transistor circuits decompilation by D. I. Cheremisinov, L. D. Cheremisinova

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Application of decision diagrams of incompletely specified of k-valued logic functions in the synthesis of logical circuits by P. N. Bibilo

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An Overview of Hybrid DC–DC Converters: From Seeds to Leaves by Yan Lu, Junwei Huang, Zhiguo Tong, Tingxu Hu, Wen-Liang Zeng, Mo Huang, Xiangyu Mao, Guigang Cai

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Controlling Underwater Robots with Electronic Nervous Systems by Joseph Ayers, Nikolai Rulkov, Dan Knudsen, Yong-Bin Kim, Alexander Volkovskii, Allen Selverston

“…We report feasibility studies of a hybrid architecture that instantiates a command and coordinating level with computed discrete-time map-based (DTM) neuronal networks and the central pattern generators with analogue VLSI (Very Large Scale Integration) electronic neuron (aVLSI) networks. …”
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Review and Selection Strategy for High-Accuracy Modeling of PWM Converters in DCM by Yu-Jun Mao, Chi-Seng Lam, Sai-Weng Sin, Man-Chung Wong, Rui Paulo Martins

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Implementation of Special Function Unit for Vertex Shader Processor Using Hybrid Number System by Avni Agarwal, P. Harsha, Swati Vasishta, S. Sivanantham

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Si1−xGex nanowire based metal‐semiconductor‐metal Schottky biristor: Design and sensitivity analysis by Shaleen Nr, Sangeeta Singh, Pankaj Kumar

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Saliency-Based Bleeding Localization for Wireless Capsule Endoscopy Diagnosis by Hongda Chen, Shaoze Wang, Yong Ding, Dahong Qian

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Estimation and Statistical Analysis of Human Voice Parameters to Investigate the Influence of Psychological Stress and to Determine the Vocal Tract Transfer Function of an Individu... by Puneet Kumar Mongia, R. K. Sharma

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A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS by Nabihah Ahmad, Rezaul Hasan

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Evaluation and Perspective of Analog Low-Dropout Voltage Regulators: A Review by Tan Yee Chyan, Harikrishnan Ramiah, S. F. Wan Muhamad Hatta, Nai Shyan Lai, Chee-Cheow Lim, Yong Chen, Pui-In Mak, Rui P. Martins

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Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model by Shupeng Wang, Kai Huang, Tianyi Xie, Xiaolang Yan

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A 12 dB 0.7 V 𝟖𝟓𝟎𝝁W CMOS LNA for 866 MHz UHF RFID Reader by Jie Li, S. M. Rezaul Hasan

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MULTIPLE FOLDING OF REGULAR STRUCTURES VIA SOLVING LOGIC EQUATIONS by L. D. Cheremisinova

“…The problem under consideration is to reduce the area of the layout of regular VLSI structures by means of their multiple folding. …”
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Advanced Power Electronic Converters and Power Quality Conditioning by Chi-Seng Lam, Yongheng Yang, Qing Zhong, Yandong Chen, Keng-Weng Lao

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Gamma Splines and Wavelets by Hannu Olkkonen, Juuso T. Olkkonen

“…Finally, we discuss the suitability of the gamma spline signal processing in embedded VLSI environment.…”
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Low Power Systolic Array Based Digital Filter for DSP Applications by S. Karthick, S. Valarmathy, E. Prabhu

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Design and implementation for partition dynamically vector quantization chip by YU Ning-mei, WANG Dong-fang, LIAO Yu-min, FU Yun-qiang

“…Partition dynamically vector quantization（PDVQ） chip was researched and produced to encode images.Before encoding,it first judged the correlation of the encoding image block,and then decided to choose the size of the image blocks.Test result shows that PDVQ chip can improve the compression rate to 27% in average by contrasting with the normal VQ,even to 64%.The size of the codebook in PDVQ chip was 256×16 byte,and all codevectors in the codebook were categorized by direction,in each category codebook codewords were sorted in the ascending order of their sum,this kind codebook architecture could reduce search range largely.The VLSI architecture of PDVQ chip was implemented based on Charter 0.35μm CMOS standard cell technology,its chip area was 2.08mm×2.08mm.Test result shows that,at 3.0V power supply,PDVQ chip can operate up to 100MHz.At this operation,its power dissipation is 295mW,and it can support real-time encoding application for 512×512 gray images at 30fame/s.…”
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