An Ultra-Low Power, Adaptive All-Digital Frequency-Locked Loop With Gain Estimation and Constant Current DCO by Imran Ali, Hamed Abbasizadeh, Muhammad Riaz Ur Rehman, Muhammad Asif, Seong Jin Oh, Young Gun Pu, Minjae Lee, Keum Cheol Hwang, Youngoo Yang, Kang-Yoon Lee

“…The proposed design is integrated in an ADPLL for BLE transceiver and it is fabricated with 1P6M TSMC 55 nm CMOS technology. The all-digital adaptive FLL is fully synthesizable and its area is <inline-formula> <tex-math notation="LaTeX">$1800~\mu \text{m}^{2}$ </tex-math></inline-formula> with 1.233 K gate count. …”
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