An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates by T. Kalavathi Devi, Sakthivel Palaniappan

“…The functionality of the proposed asynchronous design is simulated and verified using Tanner Spice (TSPICE) in 0.25 µm, 65 nm, and 180 nm technologies of Taiwan Semiconductor Manufacture Company (TSMC). The simulation result illustrates that the asynchronous design techniques have 25.21% of power reduction compared to synchronous design and work at a speed of 475 MHz.…”
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Research on <inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub></math></in... by Zhanpeng JIANG, Mingwei SUN, Hai HUANG, Jiang XU, Zhiwei LIU, Rui BAI, Zhou FANG, Jiaxing QU

“…A quadratic extended-domain finely integrated operand scanning (<inline-formula><math xmlns="http://www.w3.org/1998/Math/MathML"> <msub> <mi>F</mi> <mrow> <msup> <mi>p</mi> <mn>2</mn> </msup> </mrow> </msub> </math></inline-formula>-FIOS) modular multiplication algorithm for bilinear pairs was proposed to address the problem of low efficiency of bilinear pair operations.The algorithm effectively reduced the number of modular reductions in modular multiplication by optimizing the operation process of (AB+CD)mod P under the quadratic expansion domain.Two hardware architectures and their scheduling methods were designed to meet different application requirements.In order to improve the computational efficiency of the algorithm, the TSMC 55 nm process was used to realize the bilinear pairing operation unit.Compared with the existing literature, the designed architecture is superior to similar modular multiplication designs in performance indicators such as the first modular multiplication time, clock frequency and the area-time product, and also has certain advantages in the overall Optimal ate pair implementation.…”
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Adaptive Optimal Terminal Sliding Mode Control for T-S Fuzzy-Based Nonlinear Systems by Farzad Soltanian, Amir Parviz Valadbeigi, Jafar Tavoosi, Rahmat Aazami, Mokhtar Shasadeghi, Mohammadamin Shirkhani, Amirreza Azizi

“…This study utilizes the Takagi–Sugeno fuzzy model to represent a subset of nonlinear systems and presents an innovative adaptive approach for optimal dynamic terminal sliding mode control (TSMC). The systems under consideration encompass bounded uncertainties in parameters and actuators, as well as susceptibility to external disturbances. …”
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Output Feedback Fractional-Order Nonsingular Terminal Sliding Mode Control of Underwater Remotely Operated Vehicles by Yaoyao Wang, Jiawang Chen, Linyi Gu

“…For the 4-DOF (degrees of freedom) trajectory tracking control problem of underwater remotely operated vehicles (ROVs) in the presence of model uncertainties and external disturbances, a novel output feedback fractional-order nonsingular terminal sliding mode control (FO-NTSMC) technique is introduced in light of the equivalent output injection sliding mode observer (SMO) and TSMC principle and fractional calculus technology. …”
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Bus Implementation Using New Low Power PFSCL Tristate Buffers by Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal

“…SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. …”
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A 7-nm-Based 5R4W High-Timing Reliability Regfile Circuit by Wanlong Zhao, Yuejun Zhang, Liang Wen, Pengjun Wang

“…First, the scheme analyzed the principles of timing errors such as read/write conflicts, write errors, and read errors in the Regfile circuit; then adopted the timing separation method of independent control of the read/write process by clock double edges to solve multiport read/write conflicts, designed a mirror memory check circuit to avoid write errors caused by the word line delays, and used a phase-locked clock feedback structure to eliminate read errors caused by the data timing fluctuations; in the TSMC 7 nm FinFET process, a 64 × 74-bit 5R4W Regfile circuit was implemented using a fully customized layout. …”
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A Low-Power Ultrawideband Low-Noise Amplifier in 0.18 μm CMOS Technology by Jun-Da Chen

“…This paper presents an ultrawideband low-noise amplifier chip using TSMC 0.18 μm CMOS technology. We propose a UWB low noise amplifier (LNA) for low-voltage and low-power application. …”
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A 32 μm² MOS-Based Remote Sensing Temperature Sensor with 1.29 °C Inaccuracy for Thermal Management by Ruohan Yang, Kwabena Oppong Banahene, Bryce Gadogbe, Randall Geiger, Degang Chen

“…This paper introduces a compact NMOS-based temperature sensor designed for precise thermal management in high-performance integrated circuits. Fabricated using the TSMC 180 nm process with a 1.8 V supply, this sensor employs a single diode-connected NMOS transistor, achieving a significant size reduction and improved voltage headroom. …”
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Mutator Circuit for Memcapacitor Emulator Using Operational Transconductance Amplifiers by Mustafa Konal, Fırat Kacar

“…All simulations were conducted using LTSpice with Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm complementary metal oxide semiconductor (CMOS) process parameters. …”
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An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation by Daniel Junehee Lee, Fei Yuan, Gul N. Khan, Yushi Zhou

“…The DTC is designed in a TSMC 65 nm 1.0 V CMOS technology and analysed using Spectre with BSIM3V3 device models. …”
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Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell by Masoodur Rahman Khan, ABM Harun‐ur Rashid

“…Simulation based on a mathematical model of memristor is presented and analysed using 65 nm TSMC MOS model parameters. Corner simulations and Monte Carlo simulations are carried out to substantiate the robustness of the design against process variation. …”
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A Power-Efficient Soft-Output Detector for Spatial-Multiplexing MIMO Communications by Hsiao-Chi Wang, Tung-Lin Liu, Yuan-Wei Wu, Hsi-Pin Ma

“…The proposed detector, using TSMC 0.18 μm single-poly six-metal CMOS process with a core area of 1.17×1.17 mm2, provides fixed throughput of 45 Mbps in 64-QAM configuration, 120 Mbps in 16-QAM configuration, and 60 Mbps in QPSK configuration. …”
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A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices by Ci-Hao Wu, Tian-Sheuan Chang

“…This is achieved through a 1-D processing array, utilizing configurable SRAM addressing, thereby minimizing hardware complexities and simplifying zero skipping. Using the TSMC 40nm CMOS process, the final implementation requires merely 207.8K gates and 53.75KB SRAM. …”
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A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction by Yu-Ping Huang, Yu-Sian Lu, Wei-Zen Chen

“…An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. …”
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A Single-Inductor Bipolar-Output DC-DC Converter With Tunable Asymmetric Power Distribution Control (APDC) for AMOLED Applications by Wei-Ting Yeh, Meng-Xun Cai, Chien-Wu Tsai, Chien-Hung Tsai

“…The proposed SIBO DC-DC converter, fabricated using TSMC&#x2019;s 0.18um 1.8V/3.3V 1P6M Mixed Signal process, is suitable for load ranges from 20mA to 200mA. …”
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Flatness-Based Motion Planning and Control Strategy of a 3D Overhead Crane by Van Chung Nguyen, Hue Luu Thi, Hoa Bui Thi Khanh, Danh Huy Nguyen, Minh Nhat Vu, Tung Lam Nguyen

“…Additionally, a Fixed-Time Extended State Observer (FxTESO) is implemented to estimate states and disturbances in fixed time, and a Terminal Sliding Mode Control (TSMC) ensures robust trajectory tracking. Simulation studies and lab-scale experiments on the 3DOC demonstrate the method&#x2019;s improvements in trajectory optimization, disturbance rejection, and overall performance. …”
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A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model by Vassilis Alimisis, Dimitrios G. Arnaoutoglou, Emmanouil Anastasios Serlis, Argyro Kamperi, Konstantinos Metaxas, George A. Kyriacou, Paul P. Sotiriadis

“…The circuit designs were executed using TSMC&#x2019;s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.…”
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A Low Power CMOS UWB LNA with Sub-1V Supply Voltage and Noise Cancellation Technique by Mehdi Alinejad, Emad Ebrahimi

“…Then, the proposed amplifier has been implemented in TSMC 0.18µm RF-CMOS technology and simulated using Cadence-IC software. …”
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Analog Computing for Nonlinear Shock Tube PDE Models: Test and Measurement of CMOS Chip by Hasantha Malavipathirana, Soumyajit Mandal, Nilan Udayanga, Yingying Wang, S. I. Hariharan, Arjuna Madanayake

“…The design was realized in TSMC 180 nm CMOS technology. It has an active area of 7.38 mm<inline-formula> <tex-math notation="LaTeX">$\times 4.64$ </tex-math></inline-formula> mm and consumes 936 mW while delivering an equivalent FDTD temporal update rate of 80 MHz and an analog bandwidth of 2 MHz. …”
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Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques by Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski

“…The proposed ADPLL is implemented in TSMC 28-nm LP CMOS. The prototype generates a 24&#x2013;31-GHz output carrier with rms jitter of 237 fs while consuming only 12 mW. …”
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