Challenges to adopting adiabatic circuits for systems‐on‐a‐chip by Krishnan S. Rengarajan, Saroj Mondal, Ravindra Kapre

“…Abstract Adiabatic complementary metal–oxide–semiconductor (CMOS) circuits have been proposed as a low‐power option for CMOS systems‐on‐a‐chip (SoCs) but have not gained popularity due to practical difficulties in scaling to millions of gates. …”
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Feasibility Study and Design of a Wearable System-on-a-Chip Pulse Radar for Contactless Cardiopulmonary Monitoring by Domenico Zito, Domenico Pepe, Bruno Neri, Fabio Zito, Danilo De Rossi, Antonio Lanatà

“…A new system-on-a-chip radar sensor for next-generation wearable wireless interface applied to the human health care and safeguard is presented. …”
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FPGA Implementation of A∗ Algorithm for Real-Time Path Planning by Yuzhi Zhou, Xi Jin, Tianqi Wang

“…The specially designed 8-port cache and OPEN list array are introduced to tackle the calculation bottleneck. The system-on-a-chip (SOC) design is implemented in Xilinx Kintex-7 FPGA to evaluate A∗ accelerator. …”
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Real-Time Monitoring Method and Circuit Based on Built-In Reliability Prediction by Wenke Ren, Yanning Chen, Xiaoming Li, Xinjie Zhou, Baichen Song, Tianci Chang

“…The three reliability failure prediction circuits are compact and energy efficient, allowing for their integration into a system on a chip as IP cores that provide early warning signals before system-on-chip failure. …”
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Method for synthesizing a logic element that implements several functions simultaneously by S. I. Sovetov, S. F. Tyurin

“…Moreover, using a single LUT for a single function reduces system-on-a-chip (SoC) scalability. Therefore, the purpose of the present work is to develop a LUT structure for implementing several logic functions simultaneously on inactive transmitting transistors.Methods. …”
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A novel buffering fault‐tolerance approach for network on chip (NoC) by Nima Jafarzadeh, Ahmad Jalili, Jafar A. Alzubi, Khosro Rezaee, Yang Liu, Mehdi Gheisari, Bahram Sadeghi Bigham, Amir Javadpour

“…NoC is a network‐based communication subsystem on an integrated circuit, most typically between modules in a system on a chip (SoC). Designing a reliable NoC against failures that can prevent failure using some measures or preventing error or system failure while failure happens and proper performance became a significant concern. …”
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Empirical Mode Decomposition and Neural Networks on FPGA for Fault Diagnosis in Induction Motors by David Camarena-Martinez, Martin Valtierra-Rodriguez, Arturo Garcia-Perez, Roque Alfredo Osornio-Rios, Rene de Jesus Romero-Troncoso

“…Moreover, the overall methodology implementation into a field-programmable gate array (FPGA) allows an online and real-time operation, thanks to its parallelism and high-performance capabilities as a system-on-a-chip (SoC) solution. The detection and classification results show the effectiveness of the proposed fused techniques; besides, the high precision and minimum resource usage of the developed digital structures make them a suitable and low-cost solution for this and many other industrial applications.…”
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Monitoring the reliability of integrated circuits protection against Trojans: encoding and decoding of combinational structures by L. A. Zolotorevich, V. A. Ilyinkov

“…Integrated circuits, systems on a chip are the key links in various industrial systems and state defense systems. …”
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