Optimized Software Implementation of Keccak, Kyber, and Dilithium on RV{32,64}IM{B}{V} by Jipeng Zhang, Yuxing Yan, Junhao Huang, Çetin Kaya Koç

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An Educational RISC-V-Based 16-Bit Processor by Jecel Mattos de Assumpção, Oswaldo Hideo Ando, Hugo Puertas de Araújo, Mario Gazziro

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Efficient Hardware-Assisted Heap Memory Safety for Embedded RISC-V Systems by Hyunjae Park, Yonghae Kim, Dongwook Kang, Hongil Ju, Gaeil An, Yongwoo Kim

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Lockstep Replacement: Fault-Tolerant Design by Jan Mach, Lukas Kohutka

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Optimised Extension of an Ultra-Low-Power RISC-V Processor to Support Lightweight Neural Network Models by Qiankun Liu, Sam Amiri

Subjects: “…RISC-V…”
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A Code-Based ISE to Protect Boolean Masking in Software by Qi Tian, Hao Cheng, Chun Guo, Daniel Page, Meiqin Wang, Weija Wang

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Spike-RISC: Algorithm/ISA Co-Optimization for Efficient SNNs on RISC-V by Ipek Akdeniz, Sandy A. Wasif, Paul R. Genssler, Hussam Amrouch

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A General Framework for Accelerator Management Based on ISA Extension by Elham Cheshmikhani, Biagio Peccerillo, Andrea Mondelli, Sandro Bartolini

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Power Side-Channel Attacks on Crypto-Core Based on RISC-V ISA for High-Security Applications by Titu Mary Ignatius, Thockchom Birjit Singha, Roy Paily Palathinkal

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Real-Time Optimization of RISC-V Processors Based on Branch Prediction and Division Data Dependency by Zhiwei Jin, Hesong Di, Tingpeng Hu, Peng Wang

Subjects: “…RISC-V…”
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Exploring Low-Cost Platforms for Automatic Chess Digitization by David Mallasén, María José Belda, Alberto A. del Barrio, Fernando Castro, Katzalin Olcoz, Manuel Prieto-Matias

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Performance Characterization of Hardware/Software Communication Interfaces in End-to-End Power Management Solutions of High-Performance Computing Processors by Antonio del Vecchio, Alessandro Ottaviano, Giovanni Bambini, Andrea Acquaviva, Andrea Bartolini

Subjects: “…RISC-V…”
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Reliability Analysis of Baremetal and FreeRTOS Applications on Microchip PolarFire SoC RISC-V Multiprocessors Using High-Energy Protons by Andre M. P. Mattos, Douglas A. Santos, Luigi Dilillo

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Efficient Prefetch and Issue Scheduling Approaches for Simultaneous Multithreading Applied to Superscalar RISC-V Processor by Hananya Ribo, Shlomo Greenberg

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A High-Level Synthesis Approach for a RISC-V RV32I-Based System on Chip and Its FPGA Implementation by Onur Toker

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Chameleon: A Dataset for Segmenting and Attacking Obfuscated Power Traces in Side-Channel Analysis by Davide Galli, Giuseppe Chiari, Davide Zoni

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Optimizing BFloat16 Deployment of Tiny Transformers on Ultra-Low Power Extreme Edge SoCs by Alberto Dequino, Luca Bompani, Luca Benini, Francesco Conti

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Call Rewinding: Efficient Backward Edge Protection by Téo Biton, Olivier Gilles, Daniel Gracia Pérez, Nikolai Kosmatov, Sébastien Pillement

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Hardware-Software Stitching Algorithm in Lightweight Q-Learning System on Chip (SoC) for Shortest Path Optimization by Yahwista Salomo, Infall Syafalni, Nana Sutisna, Trio Adiono

Subjects: “…RISC-V…”
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Implementation of the TCG DICE Specification Into the Keystone TEE Framework by Enrico Bravi, Silvia Sisinni, Lorenzo Ferro, Valerio Donnini, Antonio Lioy

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