Showing 21 - 40 results of 122 for search '"International Journal of Reconfigurable Computing"', query time: 0.04s Refine Results
  1. 21
    Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics

    Exploiting Dual-Output Programmable Blocks to Balance Secure Dual-Rail Logics by Laurent Sauvage, Maxime Nassar, Sylvain Guilley, Florent Flament, Jean-Luc Danger, Yves Mathieu

    Published 2010-01-01
    “…International Journal of Reconfigurable Computing…”
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  2. 22
    Exploring Many-Core Design Templates for FPGAs and ASICs

    Exploring Many-Core Design Templates for FPGAs and ASICs by Ilia Lebedev, Christopher Fletcher, Shaoyi Cheng, James Martin, Austin Doupnik, Daniel Burke, Mingjie Lin, John Wawrzynek

    Published 2012-01-01
    “…International Journal of Reconfigurable Computing…”
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  3. 23
    Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units

    Transparent Runtime Migration of Loop-Based Traces of Processor Instructions to Reconfigurable Processing Units by João Bispo, Nuno Paulino, João M. P. Cardoso, João Canas Ferreira

    Published 2013-01-01
    “…International Journal of Reconfigurable Computing…”
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  4. 24
    An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation

    An FPGA-Based Adaptable 200 MHz Bandwidth Channel Sounder for Wireless Communication Channel Characterisation by David L. Ndzi, Kenneth Stuart, Somboon Toautachone, Yanyan Yang, Victor Dunn

    Published 2011-01-01
    “…International Journal of Reconfigurable Computing…”
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  5. 25
    Exposing End-to-End Delay in Software-Defined Networking

    Exposing End-to-End Delay in Software-Defined Networking by Ting Zhang, Bin Liu

    Published 2019-01-01
    “…International Journal of Reconfigurable Computing…”
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  6. 26
    3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans

    3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans by Vitor de Paulo, Cristinel Ababei

    Published 2010-01-01
    “…International Journal of Reconfigurable Computing…”
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  7. 27
    Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

    Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs by Shahnam Mirzaei, Ryan Kastner, Anup Hosangadi

    Published 2010-01-01
    “…International Journal of Reconfigurable Computing…”
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  8. 28
    Challenges in Clock Synchronization for On-Site Coding Digital Beamformer

    Challenges in Clock Synchronization for On-Site Coding Digital Beamformer by Satheesh Bojja Venkatakrishnan, Elias A. Alwan, John L. Volakis

    Published 2017-01-01
    “…International Journal of Reconfigurable Computing…”
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  9. 29
    Multiloop Parallelisation Using Unrolling and Fission

    Multiloop Parallelisation Using Unrolling and Fission by Yuet Ming Lam, José Gabriel F. Coutinho, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk

    Published 2010-01-01
    “…International Journal of Reconfigurable Computing…”
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  10. 30
    Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware

    Enabling Self-Organization in Embedded Systems with Reconfigurable Hardware by Christophe Bobda, Kevin Cheng, Felix Mühlbauer, Klaus Drechsler, Jan Schulte, Dominik Murr, Camel Tanougast

    Published 2009-01-01
    “…International Journal of Reconfigurable Computing…”
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  11. 31
    An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots

    An FPGA-Based Omnidirectional Vision Sensor for Motion Detection on Mobile Robots by Jones Y. Mori, Janier Arias-Garcia, Camilo Sánchez-Ferreira, Daniel M. Muñoz, Carlos H. Llanos, J. M. S. T. Motta

    Published 2012-01-01
    “…International Journal of Reconfigurable Computing…”
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  12. 32
    Multilevel Simulation of Heterogeneous Reconfigurable Platforms

    Multilevel Simulation of Heterogeneous Reconfigurable Platforms by Damien Picard, Loic Lagadec

    Published 2009-01-01
    “…International Journal of Reconfigurable Computing…”
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  13. 33
    A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips

    A Decentralised Task Mapping Approach for Homogeneous Multiprocessor Network-On-Chips by Peter Zipf, Gilles Sassatelli, Nurten Utlu, Nicolas Saint-Jean, Pascal Benoit, Manfred Glesner

    Published 2009-01-01
    “…International Journal of Reconfigurable Computing…”
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  14. 34
    Selected Papers from ReCoSoC 2008

    Selected Papers from ReCoSoC 2008 by Michael Hübner, J. Manuel Moreno, Gilles Sassatelli, Peter Zipf

    Published 2009-01-01
    “…International Journal of Reconfigurable Computing…”
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  15. 35
    Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm”

    Corrigendum to “Hardware Accelerators Targeting a Novel Group Based Packet Classification Algorithm” by O. Ahmed, S. Areibi, G. Grewal

    Published 2018-01-01
    “…International Journal of Reconfigurable Computing…”
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  16. 36
    Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic

    Object Recognition and Pose Estimation on Embedded Hardware: SURF-Based System Designs Accelerated by FPGA Logic by Michael Schaeferling, Ulrich Hornung, Gundolf Kiefer

    Published 2012-01-01
    “…International Journal of Reconfigurable Computing…”
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  17. 37
    Open SystemC Simulator with Support for Power Gating Design

    Open SystemC Simulator with Support for Power Gating Design by George Sobral Silveira, Alisson V. Brito, Helder F. de A. Oliveira, Elmar U. K. Melcher

    Published 2012-01-01
    “…International Journal of Reconfigurable Computing…”
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  18. 38
    Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing

    Exploring Shared SRAM Tables in FPGAs for Larger LUTs and Higher Degree of Sharing by Ali Asghar, Muhammad Mazher Iqbal, Waqar Ahmed, Mujahid Ali, Husain Parvez, Muhammad Rashid

    Published 2017-01-01
    “…International Journal of Reconfigurable Computing…”
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  19. 39
    RP-Ring: A Heterogeneous Multi-FPGA Accelerator

    RP-Ring: A Heterogeneous Multi-FPGA Accelerator by Shuaizhi Guo, Tianqi Wang, Linfeng Tao, Teng Tian, Zikun Xiang, Xi Jin

    Published 2018-01-01
    “…International Journal of Reconfigurable Computing…”
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  20. 40
    AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation

    AsyncBTree: Revisiting Binary Tree Topology for Efficient FPGA-Based NoC Implementation by Kizheppatt Vipin

    Published 2019-01-01
    “…International Journal of Reconfigurable Computing…”
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