EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS by S. A. Chizhik, S. P. Basalaev, V. A. Pilipenko, A. L. Khudoley, T. A. Kuznetsova, V. V. Chikunov, A. A. Suslov

“…The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. …”
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Fault diagnosis of nonlinear analog circuits using generalized frequency response function and LSSVM. by Jialiang Zhang, Yaowang Yang

“…A fault diagnosis method of nonlinear analog circuits is proposed that combines the generalized frequency response function (GFRF) and the simplified least squares support vector machine (LSSVM). …”
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Energy-efficient analog-domain aggregator circuit for RRAM-based neural network accelerators by Khaled Humood, Yihan Pan, Shiwei Wang, Alexander Serb, Themis Prodromakis

“…In this work, we introduce a novel energy-efficient analog domain aggregator system designed for RRAM-based CIM systems. The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulations and analysis. …”
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Modeling Energetic Effectiveness and Breakage Intensity in Mining and Processing Circuits on Limestone Crushing in HPGR by Agnieszka Saramak, Daniel Saramak

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A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage by Jérôme K. Folla, Maria L. Crespo, Evariste T. Wembe, Mohammad A. S. Bhuiyan, Andres Cicuttin, Bernard Z. Essimbi, Mamun B. I. Reaz

“…The equation associated with the delay was derived and the parameters that embody the speed were identified. The design has been validated by corner analysis and post‐layout simulation results in 65 nm CMOS technology process, which reveals that the proposed circuit can operate at a higher clock frequency of 20 GHz with a low‐offset of 4.45 mV and 14.28 ps propagation delay, while dissipating only 67.8 μW power consumption from 1 V supply and exhibited lowest PDP of 0.968 fJ. …”
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Use-Case-Dependent Modeling Approach for Analysis of Distributed DC Grids by Melanie Lavery, Raffael Schwanninger, Martin Marz

Subjects: “…DC grid simulation and design…”
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Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit by Bin You, Bo Yang, Xuan Wen, Liangyu Qu

“…A new ultrahigh frequency radio frequency identification (UHF RFID) reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. …”
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How effective is circuit training on physical fitness? A high-intensity study in the sport of futsal by John Paul C. Suniga, Joselito M. Custodio, Patrick John B. Roldan, Hatem A. Shlool, Mohammad Fayiz Abumoh'D

“…Material and Methods. The research design used a one group pretest-posttest design method, with participants as many as 8 futsal athletes selected using purposive sampling technique. …”
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MESO-CMOS Hybrid Circuits With Time-Multiplexing Technique for Energy and Area-Efficient Computing in Memory by Tzuping Huang, Linran Zhao, Yiming Han, Hai Li, Ian A. Young, Yaoyao Jia

“…This library is critical to realize automated design, as it allows the implementation of all the basic CMOS functions with MESO, thereby enabling MESO-CMOS hybrid design in large-scale complex circuits. …”
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Ferroelectric Transistor-Based Synaptic Crossbar Arrays: The Impact of Ferroelectric Thickness and Device-Circuit Interactions by Chunguang Wang, Sumeet Kumar Gupta

“…However, device and circuit nonideal attributes in FeFETs-based crossbar arrays cause the output currents to deviate from the expected value, which can induce error in CiM of matrix-vector multiplications (MVMs). …”
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Fault Modeling and Testing for Analog Circuits in Complex Space Based on Supply Current and Output Voltage by Hongzhi Hu, Shulin Tian, Qing Guo

“…To address the problem of fault masking in both 2D and 3D fault models, this paper proposes an effective design for testability (DFT) method. By adding redundant bypassing-components in the circuit under test (CUT), this method achieves excellent fault isolation ratio (FIR) in ambiguity group isolation. …”
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Comparative Study of Crosstalk Reduction Techniques in RF Printed Circuit Board Using FDTD Method by Rajeswari Packianathan, Raju Srinivasan

“…As a result, coupling between the adjacent lines has increased significantly, causing crosstalk to become an important concern in high-performance circuit design. In certain applications, microstriplines may be used in printed circuit boards for propagating high-speed signals, rather than striplines. …”
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Nested chirality and multimode transfer around exceptional points driven by external forces in electric circuits by Naiqiao Pan, Tian Chen, Xiangdong Zhang

“…It is shown theoretically that nested chiral behavior and multimode transfer appear in a two-dimensional non-Hermitian higher-order topological insulator with twofold degenerate second-order EPs by tuning the external forces. Furthermore, we design and fabricate the corresponding circuit networks, and experimentally observe nested chiral behavior and multimode transfer. …”
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Multi-terminal flexible DC grid circuit breaker withstands multi-lightning strike analysis by Yutao Tang, Hongchun Shu, Kai He, Yue Dai, Yu Kuang, Yiming Han, Weijie Lou

“…Abstract Lightning represents the primary threat to power grids, with approximately 80% of natural occurrences being multi-lightning strikes, which have been extensively studied and confirmed to pose even more severe hazards. Hybrid DC circuit breakers (DCCBs) exhibit promising application prospects due to their superior interruption performance. …”
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Comprehensive Analysis of a Bridged-T Pre-Equalizer Circuit for High-Speed Visible Light Communications by Siti Hajar Ab Aziz, Norhanis Aida Mohd Nor, Suriza Ahmad Zabidi

“… This paper presents a comprehensive analysis of a bridged-T equalizer circuit (BTEC) designed for a high-speed visible light communications (VLC) system. …”
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Fast and low‐power leading‐one detectors for energy‐efficient logarithmic computing by Mohammad Saeed Ansari, Shyama Gandhi, Bruce F. Cockburn, Jie Han

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A VLSI Implementation of Rank-Order Searching Circuit Employing a Time-Domain Technique by Trong-Tu Bui, Tadashi Shibata

“…Filtering function would be implemented once the location identification function has been carried out. The prototype circuit was designed and fabricated in a 0.18 μm CMOS technology. …”
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Circuit Implementation, Synchronization of Multistability, and Image Encryption of a Four-Wing Memristive Chaotic System by Guangya Peng, Fuhong Min, Enrong Wang

“…Besides, the modular equivalent circuit of four-wing memristive system is designed and the corresponding results are observed to verify its accuracy and rationality. …”
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Analysis of Printed Circuit Boards strains using finite element analysis and digital image correlation by Liviu Marsavina, Alexandru Falk, Octavian Pop

“…This paper investigates the use of digital image correlation (DIC) and finite element analysis for strain measurement on Printed Board Circuits (PCBs). Circuit boards (PCBs) are designed to mechanically support and electrically connect an electronic component assembly. …”
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Optimizing Bioleaching for Printed Circuit Board Copper Recovery: An AI-Driven RGB-Based Approach by Jordi Vives Pons, Albert Comerma, Teresa Escobet, Antonio D. Dorado, Marta I. Tarrés-Puertas

“…Recovering copper from end-of-life electronics, especially from printed circuit boards, provides significant economic benefits, reduces environmental impact, and supports a circular economy. …”
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