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481
A Companding Technique to Reduce Peak-to-Average Ratio in Discrete Multitone Wireline Receivers
Published 2024-01-01Get full text
Article -
482
RFSoC Modulation Classification With Streaming CNN: Data Set Generation & Quantized-Aware Training
Published 2025-01-01Get full text
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483
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484
A 45Gb/s Analog Multi-Tone Receiver Utilizing a 6-Tap MIMO-FFE in 22nm FDSOI
Published 2024-01-01Get full text
Article -
485
Computation of Graph Fourier Transform Centrality Using Graph Filter
Published 2024-01-01Get full text
Article -
486
Thermal Heating in ReRAM Crossbar Arrays: Challenges and Solutions
Published 2024-01-01Get full text
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487
FBMC vs. PAM and DMT for High-Speed Wireline Communication
Published 2024-01-01Get full text
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488
A Small-Area 2nd-Order Adder-Less Continuous-Time ΔΣ Modulator With Pulse Shaping FIR DAC for Magnetic Sensing
Published 2024-01-01“…This enables a single low-dropout (LDO) voltage regulator to generate both power supply and <inline-formula> <tex-math notation="LaTeX">$\text{V}_{ref}$ </tex-math></inline-formula> for the DAC. The circuit has been designed in 65-nm CMOS technology, achieving a peak 82-dB SNDR and 91-dB DR within a signal bandwidth of 20 kHz and the CT<inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma \text{M}$ </tex-math></inline-formula> consumes <inline-formula> <tex-math notation="LaTeX">$300 ~\mu \text{W}$ </tex-math></inline-formula> of power when clocked at 10.24 MHz. …”
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489
112-Gb/s DSP-Based PAM-4 Transceivers for Large-Scale Ethernet Switching Systems
Published 2024-01-01Get full text
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490
Review on Resistive Termination Techniques Driven by Wireline Channel Behaviors
Published 2024-01-01“…Their impacts vary a lot depending on the types of interconnects and the circuits. Therefore, termination impedances must be appropriately designed for the target applications. …”
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491
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492
Digital Phase-Locked Loops: Exploring Different Boundaries
Published 2024-01-01Get full text
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493
An Overview of Hybrid DC–DC Converters: From Seeds to Leaves
Published 2024-01-01Get full text
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494
High-Speed Wireline Links—Part II: Optimization and Performance Assessment
Published 2024-01-01Get full text
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495
Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications
Published 2024-01-01“…System considerations, circuit architecture, and design implementation of wireline and linear optics transceivers capable of supporting data-rates beyond 200 Gb/s are presented. …”
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496
Recent Advances in Ultrahigh-Speed Wireline Receivers With ADC-DSP-Based Equalizers
Published 2024-01-01Get full text
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497
The Problem of Spurious Emissions in 5G FR2 Phased Arrays, and a Solution Based on an Upmixer With Embedded LO Leakage Cancellation
Published 2024-01-01“…We then present some key radio architecture and circuit design considerations to help meet these emission requirements. …”
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498
System-Technology Co-Optimization for Dense Edge Architectures Using 3-D Integration and Nonvolatile Memory
Published 2024-01-01Get full text
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499
HamFET: A High-Performance Subthermionic Transistor Through Incorporating Hybrid Switching Mechanism
Published 2024-01-01Get full text
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500