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Compensation of active filter using p-q theory in photovoltaic systems
Published 2025-04-01Get full text
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464
An energy‐efficient dynamic comparator in Carbon Nanotube Field Effect Transistor technology for successive approximation register ADC applications
Published 2022-07-01“…Finally, the kickback noise of the proposed comparator is obtained as 80 μV, which shows the proper performance of the proposed comparator circuit in comparison with other reported designs.…”
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465
Impact of Frequency Heterogeneity on Mutually Synchronized Spatially Distributed 24 GHz PLLs
Published 2024-01-01Get full text
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466
Ultrawideband LNA 1960–2019: Review
Published 2021-11-01“…This article specifically studies the challenges and solutions of designing UWB LNA by reviewing topologies and techniques such as inductive peaking, noise and distortion cancellation, gm‐boosting, active inductor and notch filter. …”
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467
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An efficient loop tiling framework for convolutional neural network inference accelerators
Published 2022-01-01Get full text
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470
Ultra‐stable, low‐noise two‐stage current source concept for electronics and laser applications
Published 2017-11-01“…The obtained parameters are competitive to commercial current drivers designed for laser applications. The two‐stage current source has been successfully implemented in a fully integrated diode‐pumped solid‐state lasers.…”
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471
Low‐power 10‐bit 100 MS/s pipelined ADC in digital CMOS technology
Published 2017-11-01Get full text
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472
Pasithea-1: An Energy-Efficient Sequential Reconfigurable Array With CPU-Like Programmability
Published 2025-01-01Get full text
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473
Voltage Reference and Voltage Regulator for the Cryogenic Performance Evaluation of the 22nm FDSOI Technology
Published 2024-01-01“…Additionally, we report the impact that MOS transistor cryogenic phenomena have over these circuits and propose to take advantage of some of those phenomena in analog circuit design. …”
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474
A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices
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475
A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction
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476
An Energy-Efficient Pipeline-SAR ADC Using Linearized Dynamic Amplifiers and Input Buffer in 22nm FDSOI
Published 2025-01-01Get full text
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477
A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model
Published 2024-01-01“…The architectures were trained using Python and were compared to software-based classifiers. The circuit designs were executed using TSMC’s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.…”
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478
V2Va +: An Efficient SystemVerilog & Verilog-to-Verilog-A Translator for Accelerated Mixed-Signal Simulation
Published 2024-01-01“…These strengths underscore its significant impact and applicability in the domain of circuit design.…”
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479
Linearity Analysis of Source-Degenerated Differential Pairs for Wireline Applications
Published 2025-01-01“…This work identifies the primary sources of nonlinearity in differential pair circuits including, broadband Variable Gain Amplifiers (VGAs) and Continuous-Time Linear Equalizers (CTLEs) using circuit simulations. …”
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480
Analysis and Verilog-A Modeling of Floating-Gate Transistors
Published 2025-01-01“…Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. Designing and fabricating these circuits typically involves extensive SPICE-based simulations, yet integrating and calibrating floating-gate transistors post-fabrication is a common practice. …”
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