Comprehensive analysis of In0.53Ga0.47As SOI-FinFET for enhanced RF/wireless performance by Priyanka Agrwal, Ajay Kumar

“…Firstly, the fundamental operating principles and unique features of InGaAs-SOI-FinFET are discussed, highlighting their three-dimensional fin structure and improved electrostatic control, which contributes to enhanced electrostatic integrity and reduced leakage currents compared to traditional CMOS technologies. The linearity performance of InGaAs-SOI-FinFET focuses on parameters such as third-order intercept point (IP3) and linearity metrics in analog circuits. …”
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Non-Foster Matching Circuit Design via Tunable Inductor for VLF Receive Loop Antennas by Yalong Yan, Chao Liu, Huaning Wu, Yinghui Dong

“…A 1 ⁎ 1 m VLF receive loop antenna was designed with a CMOS switch-based tunable inductor built into the NFC. …”
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Historical perspective and opportunity for computing in memory using floating-gate and resistive non-volatile computing including neuromorphic computing by Jennifer Hasler, Arindam Basu

“…In particular, we focus on the CMOS implementations of, and comparisons between, memristor/resistive random access memory (RRAM) devices, and floating-gate (FG) devices. …”
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Systematic Equation-Based Design of a 10-Bit, 500-MS/s Single-Channel SAR A/D Converter With 2-GHz Resolution Bandwidth by Tetsuya Iizuka, Ritaro Takenaka, Hao Xu, Asad A. Abidi

“…A 10-b self-timed SAR A/D converter is designed in 28-nm FDSOI CMOS to convert at 500 MS/s. It maintains this effective number of bits across an input bandwidth of 2 GHz, because it will be used as one of eight identical converters in a time-interleaved system to reach a conversion rate of 4 GS/s. …”
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Energy-efficient analog-domain aggregator circuit for RRAM-based neural network accelerators by Khaled Humood, Yihan Pan, Shiwei Wang, Alexander Serb, Themis Prodromakis

“…The proposed circuit has been verified and tested using Virtuoso Cadence circuit tools in 180 nm CMOS technology with post-layout simulations and analysis. …”
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A PFM-Based Calibration Method for Low-Power High-Linearity Digital Pixel by Yu Cheng, Jionghan Liu, Xiyuan Wang, Hongyu Hou, Qian Jiang, Yuchun Chang

“…A 64 × 64 array prototype digital readout integrated circuit (DROIC) was fabricated using a 0.18 μm 1P6M CMOS process. Experimental results indicated that the post-calibration linearity reached 99.6% with an input current of up to 1.5 μA. …”
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Low Noise Amplifier at 60 GHz Using Low Loss On-Chip Inductors by Karthigha Balamurugan, M. Nirmala Devi, M. Jayakumar

“…The proposed work uses an inductively degenerated 3-stage common-source LNA in a 65-nm CMOS process. Simulation results show that the LNA using custom designed inductors achieves the peak gain of 17.02 dB at 56 GHz with a noise figure of 5 dB at 60 GHz for the power consumption of 10 mW. …”
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Enhancing AI-Inspired Analog Circuit Design: Optimizing Component Sizes with the Firefly Algorithm and Binary Firefly Algorithm by Trang Hoang

“… This paper explores the use of the Firefly Algorithm (FA) and its binary variant (BFA) in optimizing analog circuit component sizing, specifically as a case study for a two-stage operational amplifier (op-amp) designed with a 65nm CMOS process. Recognizing the limitations of traditional optimization approaches in handling complex analog design requirements, this study implements both FA and BFA to enhance convergence speed and accuracy within multi-dimensional search spaces. …”
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Nanosensor Data Processor in Quantum-Dot Cellular Automata by Fenghui Yao, Mohamed Saleh Zein-Sabatto, Guifeng Shao, Mohammad Bodruzzaman, Mohan Malkani

“…Quantum-dot cellular automata (QCA) is an attractive nanotechnology with the potential alterative to CMOS technology. QCA provides an interesting paradigm for faster speed, smaller size, and lower power consumption in comparison to transistor-based technology, in both communication and computation. …”
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Assessing the Static and Dynamic Sensitivity of a Commercial Off-the-Shelf Multicore Processor for Noncritical Avionic Applications by Pablo F. Ramos, Vanessa C. Vargas, Nacer-Eddine Zergainoh, Raoul Velazco

“…The target device is the Epiphany E16G301 multicore manufactured in 65 nm CMOS which integrates 16 processor cores. This device was selected due to its high performance, low power consumption, and affordability, allowing general public accessing to parallel computing. …”
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Bus Implementation Using New Low Power PFSCL Tristate Buffers by Neeta Pandey, Bharat Choudhary, Kirti Gupta, Ankit Mittal

“…SPICE simulation results using TSMC 180 nm CMOS technology parameters are included to support the theoretical formulations. …”
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Mutator Circuit for Memcapacitor Emulator Using Operational Transconductance Amplifiers by Mustafa Konal, Fırat Kacar

“…All simulations were conducted using LTSpice with Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 μm complementary metal oxide semiconductor (CMOS) process parameters. The results corroborate the effectiveness of the circuit, highlighting its potential for advanced electronic applications.…”
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A 1.25–12.5 Gbps Adaptive CTLE with Asynchronous Statistic Eye-Opening Monitor by Chen Cai, Jian-zhong Zhao, Yu-mei Zhou

“…And the inductor peaking technology is used to improve the capacity of compensation. With SMIC 28 nm CMOS process to achieve the overall design, the power consumption and core chip area are 12 mW @ 12.5 Gbps and 0.12 mm2, respectively. …”
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On broadband, linear-phase, flat group delay, all-pole, low-pass filters for high-speed, data communication by Mihai Sanduleanu, Dan Cracan

“…A tunable, 10-stage, all-pole, Papoulis, low-pass filter, occupying 0.1815 mm2 is designed and integrated as a building block in a 22 nm CMOS FDSOI receiver for 5G/6G. Each filter stage comprises of a two-stage unity gain amplifier with common mode feedback loop. …”
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A Four Quadrature Signals’ Generator with Precise Phase Adjustment by Xiushan Wu, Yanzhi Wang, Siguang An, Jianqiang Han, Ling Sun

“…The four quadrature signals’ generator with precise phase modulation has been implemented in a 0.18 μm mixed-signal and RF 1P6M CMOS technology. The size of the chip including the pads is 675 μm⁎690 μm. …”
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A 3.9 μs Settling-Time Fractional Spread-Spectrum Clock Generator Using a Dual-Charge-Pump Control Technique for Serial-ATA Applications by Takashi Kawamoto, Masato Suzuki, Takayuki Noto

“…The SSCG is fabricated in a 0.13 μm CMOS and achieves settling time of 3.91 μs faster than 8.11 μs of a conventional SSCG. …”
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Simulation and System Design of a 3D Metrology Optical System Based on a Bidirectional OLED Microdisplay by Constanze Großmann, Ute Gawronski, Martin Breibarth, Gunther Notni, Andreas Tünnermann

“…The so-called bi-directional OLED microdisplays combine light-emitting devices (AM-OLED microdisplay) and photo sensitive detectors (photodiode matrix) on one single chip based on OLED-on-CMOS-technology. Currently this kind of display is still a prototype. …”
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A 0.69-mW Subsampling NB-IoT Receiver Employing a Linearized <italic>Q</italic>-Boosted LNA by Hongyu Lu, Ahmed Gharib Gadelkarim, Jiannan Huang, Patrick P. Mercier

“…A direct-coupling derivative superposition technique where low-<inline-formula> <tex-math notation="LaTeX">$V_{t}$ </tex-math></inline-formula> and thick-gate transistors with opposite nonlinear characteristics are combined to improve the measured IIP3 by 7 dB to &#x2212;18 dBm with little NF overhead. Fabricated in 65-nm CMOS, the entire receiver, including the LNA, an S/H circuit, and a 10-bit SAR ADC, consumes only 0.69 mW while meeting NB-IoT specifications.…”
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Energy-Efficient Discrete Cosine Transform Architecture Using Reversible Logic for IoT-Enabled Consumer Electronics by Muhammad Awais, Wilayat Khan, Tallha Akram, Yunyoung Nam

“…The proposed 8-point fully parallel DCT leverages a customized datapath based on a standard cell approach, integrating pass transistor logic and a full custom layout in UMC 90 nm CMOS technology. Comprehensive validation through functional simulations and design rule checks demonstrates the architecture&#x2019;s reliability. …”
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A High Accuracy Capacitance-to-Digital Converter with Improving Nonidealities Effects by Arash Ahmadpour, Mehdi Fallah Kazemi

“…The proposed interface is designed as an integrated circuit using a standard 0.18μm CMOS technology. A worst-case capacitance error less than 0.2fF for a 10pF sensor capacitor with maximum variation of 200fF, and parasitic capacitance of up to 20pF is obtained. …”
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