The Effect of Ferroelectric/Dielectric Capacitance Ratio on Short-Term Retention Characteristics of MFMIS FeFET by Junghyeon Hwang, Giuk Kim, Hongrae Joh, Jinho Ahn, Sanghun Jeon

“…This is primarily due to their compatibility with CMOS technology and reliable switching characteristics. …”
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SAR-Assisted Energy-Efficient Hybrid ADCs by Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu

“…The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. …”
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Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s by Liping Zhong, Quan Pan

“…This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of &#x003C;<inline-formula> <tex-math notation="LaTeX">$10{^{-}10 }$ </tex-math></inline-formula> and &#x003C;<inline-formula> <tex-math notation="LaTeX">$10{^{-}12 }$ </tex-math></inline-formula> with a single-ended channel loss of 24 and 25 dB, respectively.…”
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Design of a Novel W-Sinker RF LDMOS by Xiangming Xu, Han Yu, Jingfeng Huang, Chun Wang, Wei Ji, Zhengliang Zhou, Ying Cai, Yong Wang, Pingliang Li, Peng-Fei Wang, David Wei Zhang

“…Combined with the adoption of the techniques, like grounded shield, step gate oxide, LDD optimization, and so forth, an advanced technology for RF LDMOS based on conventional 0.35 μm CMOS technology is well established. An F+A power amplifier product with frequency range of 1.8–2.1 GHz is developed for the application of 4G LTE base station and industry leading performance is achieved. …”
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Ferroelectric memory: state-of-the-art manufacturing and research by D. A. Abdullaev, R. A. Milovanov, R. L. Volkov, N. I. Borgardt, A. N. Lantsev, K. A. Vorotilov, A. S. Sigov

“…The leading FRAM technology remains the 130 nm node CMOS process developed at Texas Instruments fabs. …”
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A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product by Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta

“…HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.…”
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Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning by Salinna Abdullah, Majid Zamani, Andreas Demosthenous

“…Mapping the design on a 65-nm CMOS process led to a chip core area of <inline-formula> <tex-math notation="LaTeX">$3.88~mm^{2}$ </tex-math></inline-formula> and a power consumption of 1.91 mW when operating at a 10 MHz clock frequency.…”
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Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique by Yi Mao, Gengzhen Qi, Pui-In Mak

“…Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. …”
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Bottom-up fabrication of 2D Rydberg exciton arrays in cuprous oxide by Kinjol Barua, Samuel Peana, Arya Deepak Keni, Vahagn Mkhitaryan, Vladimir M. Shalaev, Yong P. Chen, Alexandra Boltasseva, Hadiseh Alaeian

“…To harness these nonlinearities for quantum applications, the confinement dimensions must match the Rydberg blockade size, which can reach several microns in Cu2O. Using a CMOS-compatible growth technique, this study demonstrates the bottom-up fabrication of site-selective arrays of Cu2O microparticles. …”
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Utilizing MRAMs With Low Resistance and Limited Dynamic Range for Efficient MAC Accelerator by Sateesh, Kaustubh Chakarwar, Shubham Sahay

“…Although ultra-dense magnetic memories with multi-bit capability (MLC) were proposed recently, their application in hybrid CMOS-non-volatile memory accelerators is limited due to their low dynamic range (memory window) and high cell currents (ON&#x002F;OFF-state resistance in &#x223C;k&#x2126;). …”
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The Lawfulness of Using Copyrighted Works for Generative AI Training : A Case Study of a US Lawsuit against OpenAI and Perplexity AI by Stefany Ismantara, Wilma Silalahi

“…Regarding the fulfillment of rightholders’ economic rights, a non-exclusive blanket license through Collective Management Organizations (CMOs) as stipulated in Permenkumham 15/2024 is necessary. …”
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A Radar-Based System for Detection of Human Fall Utilizing Analog Hardware Architectures of Decision Tree Model by Vassilis Alimisis, Dimitrios G. Arnaoutoglou, Emmanouil Anastasios Serlis, Argyro Kamperi, Konstantinos Metaxas, George A. Kyriacou, Paul P. Sotiriadis

“…The circuit designs were executed using TSMC&#x2019;s 90 nm CMOS process technology and the Cadence IC Suite was employed for tasks including design, schematic implementation, and post-layout simulations.…”
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Beyond 200-Gb/s PAM4 ADC and DAC-Based Transceiver for Wireline and Linear Optics Applications by Ahmad Khairi, Amir Laufer, Ilia Radashkevich, Yoel Krupnik, Jihwan Kim, Tali Warshavsky Grafi, Ajay Balankutty, Yaniv Sabag, Yoav Segal, Udi Virobnik, Mike Peng Li, Itamar Levin, Yosef Ben Ezra, Ariel Cohen

“…We showcase the silicon results of a transceiver designed in the advanced 3-nm CMOS process, which supports long-reach channels with up to 40 dB of loss at Nyquist. …”
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A Wireless Power Conversion Chain With Fully On-Chip Automatic Resonance Tuning System for Biomedical Implants by Mohammad Javad Karimi, Menghe Jin, Catherine Dehollain, Alexandre Schmid

“…The proposed system is implemented and fabricated in standard 180nm CMOS technology, with a total area of 0.339 mm2, and its operation is verified. …”
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A fault tolerant CSA in QCA technology for IoT devices by Saeid Seyedi, Hatam Abdoli

“…Quantum-dot Cellular Automata (QCA) has emerged as a promising alternative to conventional complementary metal-oxide-semiconductor (CMOS) technology due to its great potential in digital design at nanoscale levels on account of very low power consumption and very high processing speed. …”
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Design of Interface ASIC with Power-Saving Switches for Capacitive Accelerometers by Juncheng Cai, Yongbin Cai, Xiangyu Li, Shanshan Wang, Xiaowei Zhang, Xinpeng Di, Pengjun Wang

“…The design was realized using a standard 0.35 μm CMOS process, culminating in the completion of layout design and small-scale engineering fabrication. …”
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Efficient Implementation of Mahalanobis Distance on Ferroelectric FinFET Crossbar for Outlier Detection by Musaib Rafiq, Yogesh Singh Chauhan, Shubham Sahay

“…Mahalanobis distance, the multivariate equivalent of the Euclidean distance, is used to detect the outliers in the correlated data accurately and finds widespread application in fault identification, data clustering, singleclass classification, information security, data mining, etc. However, traditional CMOS-based approaches to compute Mahalanobis distance are bulky and consume a huge amount of energy. …”
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Enhancing RF Fingerprint Generation in Power Amplifiers: Unequally Spaced Multitone Design Approaches and Considerations by Chengyu Fan, Junting Deng, Ethan Chen, Vanessa Chen

“…Following that, an innovative 2-stage PA incorporating a reconfigurable class A stage with a Doherty amplifier, designed in 65-nm CMOS to generate 4096 timestamped RFFs without introducing in-band power variation, is presented. …”
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A Negative Capacitance Field-Effect Transistor with High Rectification Efficiency for Weak-Energy 2.45 GHz Microwave Wireless Transmission by Hualian Tang, Ailan Tang, Weifeng Liu, Jingxiang Huang, Jianjun Song, Wenjie Sun

“…Furthermore, it significantly outperforms CMOS rectifiers reported in the literature. This study demonstrates the superior rectification performance of the proposed NCFET under low-power density conditions, offering an efficient device solution for microwave wireless power transmission systems.…”
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A Readout Scheme for PCM-Based Analog In-Memory Computing With Drift Compensation Through Reference Conductance Tracking by Alessio Antolini, Andrea Lico, Francesco Zavalloni, Eleonora Franchi Scarselli, Antonio Gnudi, Mattia Luigi Torres, Roberto Canegallo, Marco Pasotti

“…The proposed AIMC scheme is designed and manufactured in a 90-nm STMicroelectronics CMOS technology, with the aim of adding a signed multiply-and-accumulate (MAC) computation feature to a Ge-Rich GeSbTe (GST) embedded PCM array. …”
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