Meta‐stability immunity technique for high speed SAR ADCs by L. Qiu, K. Tang, Y.J. Zheng, L. Siek

“…The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.…”
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Progress on Waveguide-Integrated Graphene Optoelectronics by Jiaqi Wang, Zhenzhou Cheng, Xuejin Li

“…Moreover, the waveguide-integrated graphene devices are fully CMOS-compatible, which makes it possible to achieve low-cost and high-density integration in the future. …”
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From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits by Leonard F. Register, Dipanjan Basu, Dharmendar Reddy

“…Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineerable device parameters on the formation and gating of interlayer coherent state.…”
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Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods by Maneesha Gupta, Urvashi Singh, Richa Srivastava

“…The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.…”
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Programmed Tool for Quantifying Reliability and Its Application in Designing Circuit Systems by N. S. S. Singh

“…As CMOS technology scales down to nanotechnologies, reliability continues to be a decisive subject in the design entry of nanotechnology-based circuit systems. …”
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A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods by Noushin Ghaderi, Hamid Reza Erfani-jazi, Mehdi Mohseni-Mirabadi

“…The designed PLL is utilized in a 0.18 μm CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. …”
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Realization of DVCCTA Based Versatile Modulator by Neeta Pandey, Rajeshwari Pandey, Aseem Sayal, Manan Tripathi

“…The functionality of the proposed circuit is verified through SPICE simulations using TSMC 0.25 μm CMOS process model parameters. The performance parameters such as power dissipation and noise for various modulator schemes are also obtained.…”
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Processing Chip for Thin Film Bulk Acoustic Resonator Mass Sensor by Pengcheng Jin, Shurong Dong, Hao Jin, Mengjun Wu

“…Aimed at portable application, a new integrated process chip for thin film bulk acoustic resonator (FBAR) mass sensor is proposed and verified with 0.18 um CMOS processing in this paper. The longitudinal mode FBAR with back-etched structure is fabricated, which has resonant frequency 1.878 GHz and factor 1200. …”
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Novel Complete Probabilistic Models of Random Variation in High Frequency Performance of Nanoscale MOSFET by Rawid Banchuin

“…The proposed models have been verified based on the 65 nm CMOS technology by using the Monte-Carlo SPICE simulations of benchmark circuits and Kolmogorov-Smirnov tests as highly accurate since they fit the Monte-Carlo-based analysis results with 99% confidence. …”
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An On-Chip Planar Inverted-F Antenna at 38 GHz for 5G Communication Applications by Syed Muhammad Ammar Ali

“…This paper presents an on-chip planar inverted-F antenna (PIFA) implemented in TSMC 180 nm CMOS process technology. The antenna operates at a 5 G millimeter-wave center frequency of 38 GHz. …”
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Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks by Po-Tsang Huang, Wei Hwang

“…Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. …”
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Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs by Veepsa Bhatia, Neeta Pandey

“…The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a power supply of 1.8 V. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. …”
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A Wide-Band High-Resolution Transmitter for Optical Isolation Amplifier by Chengying Chen, Lixia Bai, Yunrong Zhu, Tiancheng Wu

“…The circuit is tapeout with GF CMOS 0.18 μm 1P6M process with 5 V power supply. …”
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Design and implementation of high-speed scalar multiplier for multi-elliptic curve by Bin YU, Hai HUANG, Zhiwei LIU, Shilei ZHAO, Ning NA

“…Aiming at the problem that the existing scalar multiplier cannot be applied to multi-elliptic curve and the cost is expensive, a high-speed scalar multiplier was designed, applicable to two types of elliptic curves over prime fields.Firstly, in terms of the scalar multiplication, secp256r1 base points were processed with the comb algorithm, and the Shamir algorithm for ordinary points, and the Montgomery ladder algorithm for Curve25519.Secondly, the operation of point addition and point doubling was optimized, and the condition of Z=1 in point addition was simplified, thereby effectively reducing the number of calculation cycles.Lastly, a fast modular reduction algorithm of Curve25519 was designed for modular multiplication.Multiplexing was an important factor in the entire designing process.A 1022K equivalent gate was selected for the 55 nm CMOS process.This allowed ordinary point scalar multiplications performed on secp256r1 and Curve25519 respectively, calculating at the speeds of 153 000 times per second and 158 000 times per second, with the speed for secp256r1 1.9 times that of the existing designed one.…”
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Digital Simulation of Superconductive Memory System Based on Hardware Description Language Modeling by S. Narendran, J. Selvakumar

“…We have modeled a memory system using Josephson Junction to attain low power consumption using low input voltage compared to conventional Complementary Metal Oxide Semiconductor-Static Random Access Memory (CMOS-SRAM). We attained the low power by connecting a shared/common bit line and using a 1-bit memory cell. …”
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The application of organic materials used in IC advanced packaging:A review by Liu Jikang

“…To meet the increasing complexity and performance requirements of semiconductor devices, many integrated circuit (IC) advanced packaging technologies have been developed, which including flip chip (FC), bumping, fan-in wafer level packaging (FIWLP), fan-out wafer level packaging (FOWLP), 2.5D packaging (interposer), CMOS image sensor through silicon via (CIS-TSV), fan-out panel level packaging (FOPLP) and so on. …”
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Division-Free Multiquantization Scheme for Modern Video Codecs by Mousumi Das, Atahar Mostafa, Khan Wahid

“…The design is implemented on FPGA and later synthesized in CMOS 0.18 μm technology. The results show that the proposed design satisfies the requirement of all five codecs with a maximum decoding capability of 60 fps at 187 MHz on Xilinx FPGA platform for 1080 p HD video.…”
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E-k Relation of Valence Band in Arbitrary Orientation/Typical Plane Uniaxially Strained by Zhang Chao, Xu Da-Qing, Liu Shu-Lin, Liu Ning-Zhuang

“…Uniaxial strain technology is an effective way to improve the performance of the small size CMOS devices, by which carrier mobility can be enhanced. …”
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Image Denoising Using Nonlocal Means with Shape-Adaptive Patches and New Weights by Chenglin Zuo, Jun Ma, Hao Xiong, Lin Ran

“…Digital images captured from CMOS/CCD image sensors are prone to noise due to inherent electronic fluctuations and low photon count. …”
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Design and Implementation of Nanotechnology QCA Geometric Greedy Router by Lamjed Touil, Ismail Gassoumi, Abdellatif Mtibaa

“…The QCA technology is the most likely alternative to replace conventional circuits (CMOS) due to their very low power consumption and high processing speed. …”
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