Design of Efficient Full Adder in Quantum-Dot Cellular Automata by Bibhash Sen, Ayush Rajoria, Biplab K. Sikdar

“…Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. …”
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Ultrawideband LNA 1960–2019: Review by Shahab Shahrabadi

“…Its historical aspect illustrates when the idea of wideband LNA was born and how it changed to ultrawideband LNA, and its tutorial aspect discusses circuits and achievements to present optimum LNAs in Complementary MOS (CMOS), BiCMOS and High‐Electron‐Mobility Transistor (HEMT) technologies. …”
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Accuracy Assessment for the Three-Dimensional Coordinates by High-Speed Videogrammetric Measurement by Xianglei Liu, Yi Tang, Jing Ma

“…High-speed CMOS camera is a new kind of transducer to make the videogrammetric measurement for monitoring the displacement of high-speed shaking table structure. …”
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A dive into the marketing trends of 2024: insights to unlocking potential by Vladimir Zhechev

“…Various leading marketing agencies have dedicated great deal of research and analytical effort to produce reports including noteworthy marketing trends that can aid CMOs in dealing with the dynamics of the landscape. …”
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Analysis and Verilog-A Modeling of Floating-Gate Transistors by Sayma Nowshin Chowdhury, Matthew Chen, Sahil Shah

“…Floating-gate transistors provide non-volatile analog storage in standard CMOS processes and are crucial in the development of reconfigurable Systems on Chips (SoCs), programmable analog structures, analog neural networks, and mixed-signal neuromorphic circuits. …”
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Soft Error-Tolerant and Highly Stable Low-Power SRAM for Satellite Applications by Jong-Yeob Oh, Sung-Hun Jo

“…As CMOS technology has advanced, the transistor integration density of static random-access memory (SRAM) cells has increased. …”
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Energy-efficient 3D multi-band I/O interface for enhanced mobile memory communication by Ahmed Alzahmi

“…The proposed multi-band I/O (MBI) interface utilizes 3D integration, for two radio frequency band transceivers, and a CMOS driver with resistive feedback for the baseband (BB) transceiver. …”
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Wafer-Level Characterization and Monitoring Platform for Single-Photon Avalanche Diodes by Samuel Parent, Frederic Vachon, Valerie Gauthier, Steve Lamoureux, Alexandre Paquette, Jacob Deschamps, Tommy Rossignol, Nicolas Roy, Philippe Arsenault, Henri Dautet, Serge A. Charlebois, Jean-Francois Pratte

“…This is especially true for the development of SPAD arrays 3D integrated with CMOS readout electronics, where SPAD testing is required to qualify the process, independently from the final CMOS readout circuit. …”
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Near-infrared germanium PIN-photodiodes with >1A/W responsivity by Hanchen Liu, Toni P. Pasanen, Tsun Hang Fung, Joonas Isometsä, Antti Haarahiltunen, Steven Hesse, Lutz Werner, Ville Vähänissi, Hele Savin

“…., have poor spectral responsivity, or are made of expensive group III-V non-CMOS compatible materials. Here we present a nanoengineered PIN-photodiode made of CMOS-compatible germanium (Ge) that achieves a verified external quantum efficiency (EQE) above 90% over a wide wavelength range (1.2–1.6 µm) at zero bias voltage at room temperature. …”
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sThing: A Novel Configurable Ring Oscillator Based PUF for Hardware-Assisted Security and Recycled IC Detection by Saswat Kumar Ram, Sauvagya Ranjan Sahoo, Banee Bandana Das, Kamalakanta Mahapatra, Saraju P. Mohanty

“…The performance of both the proposed modified architecture, i.e., CRO PUF and CRO sensor, is evaluated in 90 nm CMOS technology. The aging tolerant feature of the proposed CRO enhances the reliability of CRO PUF. …”
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Multilayer magnetic skyrmion devices for spiking neural networks by Aijaz H Lone, Daniel N Rahimi, Hossein Fariborzi, Gianluca Setti

“…Additionally, the LIF neuron latency is in ns; thus, when integrated with the CMOS, the proposed device structures and associated systems exhibit an excellent future for energy-efficient neuromorphic computing.…”
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Low-complexity synchronizer used in OFDM-UWB system by WANG Xue-jing, LIU Liang, YE Fan, REN Jun-yan

“…According to the results of synthesis using SMIC, 0.13μm CMOS process, the proposed design can achieve the throughput requirement with only 24% gate count and 25% power consumption of the conventional four-parallelism approach.…”
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Wide-field full-Stokes polarimetry for conical light based on all-dielectric metasurface by Qing Luo, Xiaoshao Ma, Yang Guo, Yang Zhou, Junwei Ma, Weihao Yang, Longjiang Deng, Lei Bi, Jun Qin

“…Polarization camera based on CMOS sensor and nano wire-grid technology have found widespread applications in medical diagnostics, remote sensing and industrial inspection. …”
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Current Mode Full-Wave Rectifier Based on a Single MZC-CDTA by Neeta Pandey, Rajeshwari Pandey

“…The functionality of the circuit is verified with SPICE simulation using 0.35 μm TSMC CMOS technology parameters.…”
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Passive On-Chip Components for Fully Integrated Silicon RF VCOs by Aristides Kyranas, Yannis Papananos

“…Design examples of passive devices operating at 5 and 6 GHz in a commercial HBT BiCMOS process are also presented. The parallel resonator quality factor is computed as a function of inductor L capacitor C and their respective losses RSL and RSC .…”
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Cascadable Current-Mode First-Order All-Pass Filter Based on Minimal Components by Jitendra Mohan, Sudhanshu Maheshwari

“…The theoretical results are verified using PSPICE simulation program with TSMC 0.35 μm CMOS process parameters.…”
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Research and design of parallel architecture processor for elliptic curve cryptography by YANG Xiao-hui, DAI Zi-bin, LI Miao, ZHANG Yong-fu

“…Based on the analysis of the ECC algorithms processing structure characteristics and parallel schedule on finite field level,a parallel architecture processor model for ECC was proposed which adopting the ILP and DLP.A prototype has been implemented based on the parallel architecture processor model.And storage structure in the model is also analyzed.The prototype is realized using FPGA,and synthesis,place and route have been accomplished under 0.18μm CMOS technology.The results prove that the proposed parallel architecture processor for ECC can guarantee high flexibility for arbitrary ECC algorithms and can achieve high performance.…”
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Gm-Realization of Controlled-Gain Current Follower Transconductance Amplifier by Worapong Tangsrirat

“…The circuit is designed and analyzed in 0.35 μm TSMC CMOS technology. Simulation results for the circuit with ±1.25 V supply voltages show that it consumes only 0.43 mw quiescent power with 70 MHz bandwidth. …”
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Static Switching Dynamic Buffer Circuit by A. K. Pandey, R. A. Mishra, R. K. Nagaria

“…Simulation is done using 0.18 µm CMOS technology. We have calculated the power consumption, delay, and power delay product of the proposed circuit and compared the results with the existing circuits for different logic function, loading condition, clock frequency, temperature, and power supply. …”
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VM and CM Universal Filters Based on Single DVCCTA by Neeta Pandey, Sajal K. Paul

“…SPICE simulation using 0.25 μm TSMC CMOS technology parameters is included to show the workability of the proposed circuits.…”
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