Fully Integrated Chen Chaotic Oscillation System by Ziyi Ouyang, Jie Jin, Fei Yu, Long Chen, Lei Ding

“…Unlike the conventional breadboard-based Chen chaotic system using off-the-shelf discrete components, the fully integrated Chen chaotic oscillation circuit presented in this paper is realized using GlobalFoundries’ 0.18 μm CMOS 1P6M process, and all the circuit components are integrated in a chip. …”
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A ± 1.55ppm Stable FBAR Reference Clock with Oven-Controlled Temperature Compensation by Jabeom Koo, Kannan Sankaragomathi, Richard Ruby, Brian Otis

“…The highly integrated system includes a 0.64mm2 FBAR chip with integrated heater and sensor resistors and a 3 mm2 CMOS chip with the control electronics. The oscillator achieves an Allen deviation of 4ppb enabled by a temperature-to-digital converter (TDC) with a 150uK resolution. …”
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Mechanism of Threshold Voltage Instability in Double Gate α-IGZO Nanosheet TFT Under Bias and Temperature Stress by Muhammad Aslam, Shu-Wei Chang, Yi-Ho Chen, Yao-Jen Lee, Yiming Li, Wen-Hsi Lee

“…ABSTRACT Amorphous indium gallium zinc oxide (a-IGZO)-based thin film transistors (TFTs) are increasingly becoming popular because of their potential in futuristic applications, including CMOS technology. Given the demand for CMOS-compatible, ultra-scaled, reliable, and high-performing devices, we fabricate and analyze scaled-channel a-IGZO-TFTs with an optimal double-gate structure, a thin nanosheet-based channel, and an effective high- <inline-formula> <tex-math notation="LaTeX">$\kappa$ </tex-math></inline-formula> dielectric namely HfO2. …”
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Heterogeneous integration of amorphous silicon carbide on thin film lithium niobate by Zizheng Li, Naresh Sharma, Bruno Lopez-Rodriguez, Roald van der Kolk, Thomas Scholte, Hugo Voncken, Jasper van der Boom, Simon Gröblacher, Iman Esmaeil Zadeh

“…Despite numerous demonstrations of high-performance LN photonics, processing lithium niobate remains challenging and suffers from incompatibilities with standard complementary metal–oxide–semiconductor (CMOS) fabrication lines, limiting its scalability. …”
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Characteristics and Breakdown Behaviors of Polysilicon Resistors for High Voltage Applications by Xiao-Yu Tang, Ke Dong

“…With the rapid development of the power integrated circuit technology, polysilicon resistors have been widely used not only in traditional CMOS circuits, but also in the high voltage applications. …”
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Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures by Francesca Palumbo, Tiziana Fanni, Carlo Sau, Paolo Meloni, Luigi Raffo

“…Experimental results, on 90 and 45 nm CMOS technologies, demonstrate that the proposed approach guides the designer towards optimal implementation.…”
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Fully Integrated Memristor and Its Application on the Scroll-Controllable Hyperchaotic System by Jie Jin, Li Cui

“…The fully integrated memristor and memristor-based hyperchaotic system are verified with the GlobalFoundries’ 0.18 μm CMOS process using Cadence IC Design Tools. The postlayout simulation results demonstrate that the memristor-based fully integrated hyperchaotic system consumes 90.5 mW from ±2.5 V supply voltage and it takes a compact chip area of 1.8 mm2.…”
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Meta‐stability immunity technique for high speed SAR ADCs by L. Qiu, K. Tang, Y.J. Zheng, L. Siek

“…The ADC chip was fabricated in a 65 nm CMOS technology. It achieves an ENOB of 7.45 bits, with 48 mW power consumption and an area of 0.075 mm2.…”
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Progress on Waveguide-Integrated Graphene Optoelectronics by Jiaqi Wang, Zhenzhou Cheng, Xuejin Li

“…Moreover, the waveguide-integrated graphene devices are fully CMOS-compatible, which makes it possible to achieve low-cost and high-density integration in the future. …”
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From Coherent States in Adjacent Graphene Layers toward Low-Power Logic Circuits by Leonard F. Register, Dipanjan Basu, Dharmendar Reddy

“…Here we review the basic BiSFET device concept and ongoing efforts to determine how such a device, which would be far from a drop-in replacement for MOSFETs in CMOS logic, could be used for low-power logic operation, and to model the effects of engineerable device parameters on the formation and gating of interlayer coherent state.…”
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Bandwidth Extension of High Compliance Current Mirror by Using Compensation Methods by Maneesha Gupta, Urvashi Singh, Richa Srivastava

“…The circuits are designed in TSMC 0.18 μm CMOS technology on Spectre simulator of Cadence.…”
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Programmed Tool for Quantifying Reliability and Its Application in Designing Circuit Systems by N. S. S. Singh

“…As CMOS technology scales down to nanotechnologies, reliability continues to be a decisive subject in the design entry of nanotechnology-based circuit systems. …”
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A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods by Noushin Ghaderi, Hamid Reza Erfani-jazi, Mehdi Mohseni-Mirabadi

“…The designed PLL is utilized in a 0.18 μm CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. …”
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Realization of DVCCTA Based Versatile Modulator by Neeta Pandey, Rajeshwari Pandey, Aseem Sayal, Manan Tripathi

“…The functionality of the proposed circuit is verified through SPICE simulations using TSMC 0.25 μm CMOS process model parameters. The performance parameters such as power dissipation and noise for various modulator schemes are also obtained.…”
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Processing Chip for Thin Film Bulk Acoustic Resonator Mass Sensor by Pengcheng Jin, Shurong Dong, Hao Jin, Mengjun Wu

“…Aimed at portable application, a new integrated process chip for thin film bulk acoustic resonator (FBAR) mass sensor is proposed and verified with 0.18 um CMOS processing in this paper. The longitudinal mode FBAR with back-etched structure is fabricated, which has resonant frequency 1.878 GHz and factor 1200. …”
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Novel Complete Probabilistic Models of Random Variation in High Frequency Performance of Nanoscale MOSFET by Rawid Banchuin

“…The proposed models have been verified based on the 65 nm CMOS technology by using the Monte-Carlo SPICE simulations of benchmark circuits and Kolmogorov-Smirnov tests as highly accurate since they fit the Monte-Carlo-based analysis results with 99% confidence. …”
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An On-Chip Planar Inverted-F Antenna at 38 GHz for 5G Communication Applications by Syed Muhammad Ammar Ali

“…This paper presents an on-chip planar inverted-F antenna (PIFA) implemented in TSMC 180 nm CMOS process technology. The antenna operates at a 5 G millimeter-wave center frequency of 38 GHz. …”
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Self-Calibrated Energy-Efficient and Reliable Channels for On-Chip Interconnection Networks by Po-Tsang Huang, Wei Hwang

“…Furthermore, this technique tolerates timing variations. Based on UMC 65 nm CMOS technology, the proposed channels reduces energy consumption by nearly 28.3% compared with that for uncoded channels at the lowest voltage. …”
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Modified Tang and Pun’s Current Comparator and Its Application to Full Flash and Two-Step Flash Current Mode ADCs by Veepsa Bhatia, Neeta Pandey

“…The theoretical propositions are verified through spice simulation using 0.18 μm TSMC CMOS technology at a power supply of 1.8 V. Propagation delay, power dissipation, and power delay product (PDP) have been calculated for the proposed current comparator and process parameter variation has been studied. …”
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A Wide-Band High-Resolution Transmitter for Optical Isolation Amplifier by Chengying Chen, Lixia Bai, Yunrong Zhu, Tiancheng Wu

“…The circuit is tapeout with GF CMOS 0.18 μm 1P6M process with 5 V power supply. …”
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