Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell by Masoodur Rahman Khan, ABM Harun‐ur Rashid

Subjects: “…CMOS memory circuits…”
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8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox by Pingda Guan, Haikun Jia, Wei Deng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi

Subjects: “…CMOS…”
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Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at <italic>K/Ka</italic>- and <italic>E/W</italic>-Band by Sungwon Kwon, Minjae Jung, Byung-Wook Min

Subjects: “…CMOS integrated circuits…”
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TVD‐PB logic circuit based on camouflaging circuit for IoT security by Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu

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A 32 μm² MOS-Based Remote Sensing Temperature Sensor with 1.29 °C Inaccuracy for Thermal Management by Ruohan Yang, Kwabena Oppong Banahene, Bryce Gadogbe, Randall Geiger, Degang Chen

Subjects: “…complementary metal oxide semiconductor (CMOS) temperature sensor…”
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A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage by Jérôme K. Folla, Maria L. Crespo, Evariste T. Wembe, Mohammad A. S. Bhuiyan, Andres Cicuttin, Bernard Z. Essimbi, Mamun B. I. Reaz

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Canonization of graphs during transistor circuits decompilation by D. I. Cheremisinov, L. D. Cheremisinova

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Design of 10T SRAM cell with improved read performance and expanded write margin by Ashish Sachdeva, V. K. Tomar

Subjects: “…CMOS memory circuits…”
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A 0.6 V 2.7 mW 94.3% locking range injection‐locked frequency divider using modified varactor‐less Colpitts oscillator topology by Zhen Li, Zhenrong Li, Xing Quan, Zeyuan Wang, Xinyu Li, Yiqi Zhuang

Subjects: “…CMOS integrated circuits…”
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A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) by Ali H. Hassan, Hassan Mostafa, Mohamed Refky, Khaled N. Salama, Ahmed M. Soliman

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Optimizing the Electrical Interface for Large-Scale Color-Center Quantum Processors by Luc Enthoven, Masoud Babaie, Fabio Sebastiano

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Toward Fine-Grained Partitioning of Low-Level SRAM Caches for Emerging 3D-IC Designs by Sudipta Das, Bhawana Kumari, Siva Satyendra Sahoo, Yukai Chen, James Myers, Dragomir Milojevic, Dwaipayan Biswas, Julien Ryckaert

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Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures by Shivendra Singh Parihar, Girish Pahwa, Baker Mohammad, Yogesh Singh Chauhan, Hussam Amrouch

Subjects: “…cryogenic complementary metal–oxide–semiconductor (CMOS)…”
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Low-power artificial neuron networks with enhanced synaptic functionality using dual transistor and dual memristor. by Keerthi Nalliboyina, Sakthivel Ramachandran

“…The simulations were carried out using the Spectre tool with 45 nm CMOS technology.…”
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Saber With Hybrid Striding Toom Cook-Based Multiplier: Implementation Using Open-Source Tool Flow and Industry Standard Chip Design Tools by Muhammad Naveed Abbasi, Abdul Rehman Aslam, Muhammad Awais Bin Altaf, Wala Saadeh

“…The implemented design is realized utilizing Cadence digital-flow (industry-standard) and open-source tool flow (OFRS) with CMOS 180nm TSMC and CMOS (130nm/180nm SKY-WATER) process, respectively. …”
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Technology and Modeling of Nonclassical Transistor Devices by George V. Angelov, Dimitar N. Nikolov, Marin H. Hristov

“…In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.…”
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VLSI design of an irregular LDPC decoder in DTMB by CHEN Yun, ZENG Xiao-yang, LIN Yi-fan, XIANG Bo, DENG Yun-song

“…An irregular LDPC decoder with a code length of 7 493 bits for DTMB system was implemented based on SMIC 0.13μm CMOS process.A new method to control memories was proposed,which can reuse memories for three different code rates only by increasing 5% memory usage.The throughput of the LDPC decoder is up to 150Mbit/s with the max iterative number of 15.While keeping the throughout of 50Mbit/s,its max iterative number can reach 45.The FPGA synthesis reports and the decoder layout in SMIC 0.13μm CMOS technology are given.…”
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Cryogenic III-V and Nb electronics integrated on silicon for large-scale quantum computing platforms by Jaeyong Jeong, Seong Kwang Kim, Yoon-Je Suh, Jisung Lee, Joonyoung Choi, Joon Pyo Kim, Bong Ho Kim, Juhyuk Park, Joonsup Shim, Nahyun Rheem, Chan Jik Lee, Younjung Jo, Dae-Myeong Geum, Seung-Young Park, Jongmin Kim, Sanghyeon Kim

“…Recent results in high-fidelity spin qubits manufactured with a Si CMOS technology, along with demonstrations that cryogenic CMOS-based control/readout electronics can be integrated into the same chip or die, opens up an opportunity to break out the challenges of qubit size, I/O, and integrability. …”
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Power‐jitter trade‐off analysis in digital‐to‐time converters by A. Santiccioli, C. Samori, A.L. Lacaita, S. Levantino

“…The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current‐mode ones only when their output range is lower than about 1.4 times the clock period.…”
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New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic by Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta

“…Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.…”
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