Pass-Transistor-Enabled Split Input Voltage Level Shifter for Ultra-Low-Power Applications by Chakali Chandrasekhar, Mohammed Mahaboob Basha, Sari Mohan Das, Oruganti Hemakesavulu, Mohan Dholvan, Javed Syed

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An 8‐bit digital‐to‐time converter with pre‐skewing and time interpolation by Daniel Junehee Lee, Fei Yuan, Gul N. Khan, Yushi Zhou

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Memristor‐transistor hybrid ternary content addressable memory using ternary memristive memory cell by Masoodur Rahman Khan, ABM Harun‐ur Rashid

Subjects: “…CMOS memory circuits…”
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8-Shaped Inductors: An Essential Addition to RFIC Designers’ Toolbox by Pingda Guan, Haikun Jia, Wei Deng, Teerachot Siriburanon, Robert Bogdan Staszewski, Zhihua Wang, Baoyong Chi

Subjects: “…CMOS…”
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Ultra-Wideband 4-Bit Distributed Phase Shifters Using Lattice Network at <italic>K/Ka</italic>- and <italic>E/W</italic>-Band by Sungwon Kwon, Minjae Jung, Byung-Wook Min

Subjects: “…CMOS integrated circuits…”
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TVD‐PB logic circuit based on camouflaging circuit for IoT security by Yuejun Zhang, Qiufeng Wu, Pengjun Wang, Liang Wen, Zhicun Luan, Chongyan Gu

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A 32 μm² MOS-Based Remote Sensing Temperature Sensor with 1.29 °C Inaccuracy for Thermal Management by Ruohan Yang, Kwabena Oppong Banahene, Bryce Gadogbe, Randall Geiger, Degang Chen

Subjects: “…complementary metal oxide semiconductor (CMOS) temperature sensor…”
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A low‐offset low‐power and high‐speed dynamic latch comparator with a preamplifier‐enhanced stage by Jérôme K. Folla, Maria L. Crespo, Evariste T. Wembe, Mohammad A. S. Bhuiyan, Andres Cicuttin, Bernard Z. Essimbi, Mamun B. I. Reaz

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Canonization of graphs during transistor circuits decompilation by D. I. Cheremisinov, L. D. Cheremisinova

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Design of 10T SRAM cell with improved read performance and expanded write margin by Ashish Sachdeva, V. K. Tomar

Subjects: “…CMOS memory circuits…”
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A 0.6 V 2.7 mW 94.3% locking range injection‐locked frequency divider using modified varactor‐less Colpitts oscillator topology by Zhen Li, Zhenrong Li, Xing Quan, Zeyuan Wang, Xinyu Li, Yiqi Zhuang

Subjects: “…CMOS integrated circuits…”
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A 0.002‐mm2 8‐bit 1‐MS/s low‐power time‐based DAC (T‐DAC) by Ali H. Hassan, Hassan Mostafa, Mohamed Refky, Khaled N. Salama, Ahmed M. Soliman

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Optimizing the Electrical Interface for Large-Scale Color-Center Quantum Processors by Luc Enthoven, Masoud Babaie, Fabio Sebastiano

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Low-power artificial neuron networks with enhanced synaptic functionality using dual transistor and dual memristor. by Keerthi Nalliboyina, Sakthivel Ramachandran

“…The simulations were carried out using the Spectre tool with 45 nm CMOS technology.…”
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Technology and Modeling of Nonclassical Transistor Devices by George V. Angelov, Dimitar N. Nikolov, Marin H. Hristov

“…In view of that, compact modeling of bulk CMOS transistors and multiple-gate transistors are considered as well as BSIM and PSP multiple-gate models, FD-SOI MOSFETs, CNTFET, and SET modeling are reviewed.…”
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Power‐jitter trade‐off analysis in digital‐to‐time converters by A. Santiccioli, C. Samori, A.L. Lacaita, S. Levantino

“…The jitter‐power product is analysed and shown to scale up linearly as the full‐scale delay range in current‐mode logic implementations, and quadratically in CMOS logic. It is also shown that CMOS converters outperforms current‐mode ones only when their output range is lower than about 1.4 times the clock period.…”
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New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic by Kirti Gupta, Ranjana Sridhar, Jaya Chaudhary, Neeta Pandey, Maneesha Gupta

“…Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.…”
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Design of Efficient Full Adder in Quantum-Dot Cellular Automata by Bibhash Sen, Ayush Rajoria, Biplab K. Sikdar

“…Further downscaling of CMOS technology becomes challenging as it faces limitation of feature size reduction. …”
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Ultrawideband LNA 1960–2019: Review by Shahab Shahrabadi

“…Its historical aspect illustrates when the idea of wideband LNA was born and how it changed to ultrawideband LNA, and its tutorial aspect discusses circuits and achievements to present optimum LNAs in Complementary MOS (CMOS), BiCMOS and High‐Electron‐Mobility Transistor (HEMT) technologies. …”
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Accuracy Assessment for the Three-Dimensional Coordinates by High-Speed Videogrammetric Measurement by Xianglei Liu, Yi Tang, Jing Ma

“…High-speed CMOS camera is a new kind of transducer to make the videogrammetric measurement for monitoring the displacement of high-speed shaking table structure. …”
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