A 128 Gbps PAM‐4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS by Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang

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An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology by Hemad Heidari Jobaneh

“…Advanced design system and TSMC 0.18 µm CMOS process are utilized to carry on the simulation.…”
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The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology by Hemad Heidari Jobaneh

“…In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. …”
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Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach by Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh

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Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process by E. Kim, T. Oh

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A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS by Rui Ma, Florian Protze, Frank Ellinger

“…A proof‐of‐concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45‐nm RF‐SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. …”
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A 1–5 GHz 22 mW receiver frontend with active‐feedback baseband and voltage‐commutating mixers in 65 nm CMOS by Benqing Guo, Haishi Wang, Huifen Wang, Lei Li, Wanting Zhou, Kianoosh Jalali

“…Abstract A CMOS baseband‐active‐feedback receiver frontend with passive voltage‐commutating mixers is proposed. …”
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Multi-Channel PWM Heater Control Chip in 0.18 μm High-Voltage CMOS for a Quantum Simulator by Christoph Ribisch, Michael Hofbauer, Kerstin Schneider-Hornstein, Alexander Kuttner, Martin Jungwirth, Horst Zimmermann

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A 70-MHz Bandwidth Time-Interleaved Noise-Shaping SAR-Assisted Delta-Sigma ADC With Digital Cross-Coupling in 28-nm CMOS by Lucas Moura Santana, Ewout Martens, Jorge Lagos, Piet Wambacq, Jan Craninckx

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Single event transient mitigation techniques for a cross‐coupled LC oscillator, including a single‐event transient hardened CMOS LC‐VCO circuit by Arumugam Karthigeyan, Sankararajan Radha, Esakkimuthu Manikandan

“…This study proposes techniques to mitigate SETs in CMOS voltage‐controlled oscillators (VCOs) without affecting the circuit specifications. …”
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A 0.8 V 0.23 nW 1.5 ns Full-Swing Pass-Transistor XOR Gate in 130 nm CMOS by Nabihah Ahmad, Rezaul Hasan

“…The XOR gate utilizes six transistors to achieve a compact circuit design and was fabricated using the 130 nm IBM CMOS process. The performance of the XOR circuit was validated against other XOR gate designs through simulations using the same 130 nm CMOS process. …”
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Improved voltage transfer method for lithium battery string management chip by Kai‐Kai Wu, Hong‐Yi Wang, Chen Chen, Tao Tao, You‐You Fan, Hao Zhang, Yu‐Xin Liu

Subjects: “…CMOS integrated circuits…”
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Memory State Dynamics in BEOL FeFETs: Impact of Area Ratio on Analog Write Mechanisms and Charging by Hannes Dahlberg, Oscar Kaatranen, Karl-Magnus Persson, Arto Rantala, Jacek Flak, Lars-Erik Wernersson

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Challenges to adopting adiabatic circuits for systems‐on‐a‐chip by Krishnan S. Rengarajan, Saroj Mondal, Ravindra Kapre

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A 28-GHz CMOS-65 nm Dual Mode Class-J Doherty Power Amplifier With Integrated Class-G Driver and Impedance-Modulated- Quadrature-Transformer Achieving 21% Back-Off Efficiency by Selvakumar Mariappan, Jagadheswaran Rajendran, Norhamizah Idros, Sofiyah Sal Hamid, Asrulnizam Bin Abd Manaf, Narendra Kumar, Abdullah Alghaihab, Arokia Nathan, Binboga Siddik Yarman

Subjects: “…CMOS…”
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Fully implantable, multi‐channel microstimulator with tracking supply ribbon, multi‐output charge pump and energy recovery by Amin Rashidi, Niloofar Yazdani, Amir M. Sodagar

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Modeling and Experimental Validation of the Intrinsic SNR in Spin Qubit Gate-Based Readout and Its Impacts on Readout Electronics by Bagas Prabowo, Jurgen Dijkema, Xiao Xue, Fabio Sebastiano, Lieven M. K. Vandersypen, Masoud Babaie

Subjects: “…Cryo-CMOS…”
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Analysis of GAA Junction Less NS FET Towards Analog and RF Applications at 30 nm Regime by Asisa Kumar Panigrahy, Sudheer Hanumanthakari, Shridhar B. Devamane, Shruti Bhargava Choubey, M. Prasad, D. Somasundaram, N. Kumareshan, N. Arun Vignesh, Gnanasaravanan Subramaniam, Durga Prakash M, Raghunandan Swain

Subjects: “…CMOS inverter…”
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A −11.6-dBm OMA Sensitivity 0.55-pJ/bit 40-Gb/s Optical Receiver Designed Using a 2-Port-Parameter-Based Design Methodology by Yongxin Li, Tianyu Wang, Mostafa Gamal Ahmed, Ruhao Xia, Kyu-Sang Park, Mahmoud A. Khalil, Sashank Krishnamurthy, Zhe Xuan, Ganesh Balamurugan, Pavan Kumar Hanumolu

Subjects: “…CMOS…”
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Digital Phase-Locked Loops: Exploring Different Boundaries by Yuncheng Zhang, Dingxin Xu, Kenichi Okada

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