截止频率可调的CMOS低电压低功率高通滤波器 by 李树涛, 何怡刚, 吴杰

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System-level modeling with temperature compensation for a CMOS-MEMS monolithic calorimetric flow sensing SoC by Linze Hong, Ke Xiao, Xiangyu Song, Liwei Lin, Wei Xu

“…Abstract We present a system-level model with an on-chip temperature compensation technique for a CMOS-MEMS monolithic calorimetric flow sensing SoC. …”
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A Low Power CMOS UWB LNA with Sub-1V Supply Voltage and Noise Cancellation Technique by Mehdi Alinejad, Emad Ebrahimi

“…Then, the proposed amplifier has been implemented in TSMC 0.18µm RF-CMOS technology and simulated using Cadence-IC software. …”
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Microwave Imaging Using CMOS Integrated Circuits with Rotating 4 × 4 Antenna Array on a Breast Phantom by Hang Song, Afreen Azhari, Xia Xiao, Eiji Suematsu, Hiromasa Watanabe, Takamaro Kikkawa

“…Gaussian monocycle pulses are generated by CMOS logic circuits and transmitted by a 4 × 4 matrix antenna array via two CMOS single-pole-eight-throw (SP8T) switching matrices. …”
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An Analysis of Temperature-Dependent Timing Jitter Factors in the Structural Design of Complementary Metal-Oxide-Semiconductor Single-Photon Avalanche Detectors by Jau-Yang Wu, Yu-Wei Lu, Meng-Hsuan Liu, Tien-Ning Chang, Chun-Hsien Liu

Subjects: “…CMOS SPAD…”
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Performance Optimization of Fabricated Nanosheet GAA CMOS Transistors and 6T-SRAM Cells via Source/Drain Doping Engineering by Xuexiang Zhang, Qingkun Li, Lei Cao, Qingzhu Zhang, Renjie Jiang, Peng Wang, Jiaxin Yao, Huaxiang Yin

“…These results indicate that the optimization to S/D doping engineering may achieve substantial performance gains in both the GAA CMOS transistors and the SRAM cells.…”
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一种全CMOS工艺吉比特以太网串并-并串转换电路 by 朱正, 邱祖江, 任俊彦, 杨莲兴

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A 12 GHz 30 mW 130 nm CMOS Rotary Travelling Wave Voltage Controlled Oscillator by G. Jacquemod, F. Ben Abdeljelil, L. Carpineto, W. Tatinian, M. Borgarino

“…This paper reports a 12 GHz rotary travelling wave (RTW) voltage controlled oscillator designed in a 130 nm CMOS technology. The phase noise and power consumption performances were compared with the literature and with telecommunication standards for broadcast satellite applications. …”
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A 12 dB 0.7 V 𝟖𝟓𝟎𝝁W CMOS LNA for 866 MHz UHF RFID Reader by Jie Li, S. M. Rezaul Hasan

“…The design of a narrow-band cascode CMOS inductive source-degenerated low noise amplifier (LNA) for 866 MHz UHF RFID reader is presented. …”
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Realization of 10bit, 200MHz sampling frequency CMOS video D/A converter with gradient error compensation by HUANG Jiao-ying1, HE Yi-gang1 YANG Hui1, TANG Sheng-xue1, SHEN Fang1

“…A circuit of 10bit,200MHz sampling frequency current steering DAC with hierarchical symmetrical switching sequences was presented,which compensate the gradient error.The DAC employs segmented architecture.An integral linearity error caused by error distributes of current sources was reduced by a new switching sequence called "hierarchi-cal symmetrical switching".The DAC was built in a video-rate adaptive equalizer IC,which was fabricated in a 0.35μm,3.3V CMOS process.The area of DAC is 1.26mm×0.78mm.When operating at 14.318 MHz（4Fsc） sampling freguency,the effective numbers of bits is 9.3.Both the integral and the differential linearity errors are less than ± 0.5LSB.…”
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Investigation and Analysis of the Simultaneous Switching Noise in Power Distribution Network with Multi-Power Supplies of High Speed CMOS Circuits by Khaoula Ait Belaid, Hassan Belahrach, Hassan Ayad

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A Low-Power and Low-Noise 4-12 GHz Buck CMOS Low-Noise Amplifier with Current-Reused Technique by J. Liu, L. Li

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A 128 Gbps PAM‐4 feed forward equaliser with optimized 1UI pulse generator in 65 nm CMOS by Jiawei Wang, Hao Xu, Ziqiang Wang, Haikun Jia, Hanjun Jiang, Chun Zhang, Zhihua Wang

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An Approach to Increase Power-Added Efficiency in a 5 GHz Class E Power Amplifier in 0.18 µm CMOS Technology by Hemad Heidari Jobaneh

“…Advanced design system and TSMC 0.18 µm CMOS process are utilized to carry on the simulation.…”
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An Ultra-Low-Power Static Contention-Free 25-Transistor True Single-Phase-Clocked Flip-Flop in 55 nm CMOS by Jiliang Liu, Huidong Zhao, Zhi Li, Kangning Wang, Shushan Qiao

Subjects: “…CMOS digital circuits…”
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The Design of an Ultralow-Power Ultra-wideband (5 GHz–10 GHz) Low Noise Amplifier in 0.13 μm CMOS Technology by Hemad Heidari Jobaneh

“…In addition, TSMC 0.13 μm CMOS process is used in ADS. The LNA is biased with two different voltage supplies in order to reduce power consumption. …”
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Impact of Strain on Sub-3 nm Gate-All-Around CMOS Logic Circuit Performance Using a Neural Compact Modeling Approach by Ji Hwan Lee, Kihwan Kim, Kyungjin Rim, Soogine Chong, Hyunbo Cho, Saeroonter Oh

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Single‐ended 2 ch. × 3.4 Gbit/s dual‐mode near‐ground transmitter IO driver in 45 nm CMOS process by E. Kim, T. Oh

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A 5.5–7.5‐GHz band‐configurable wake‐up receiver fully integrated in 45‐nm RF‐SOI CMOS by Rui Ma, Florian Protze, Frank Ellinger

“…A proof‐of‐concept WuRX circuit occupying an area of 1200 μm by 900 μm has been fabricated in a GlobalFoundries 45‐nm RF‐SOI CMOS technology. Measurement results show that at a data rate of 64 bps, the entire WuRX consumes only 2.3 μW. …”
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A 1–5 GHz 22 mW receiver frontend with active‐feedback baseband and voltage‐commutating mixers in 65 nm CMOS by Benqing Guo, Haishi Wang, Huifen Wang, Lei Li, Wanting Zhou, Kianoosh Jalali

“…Abstract A CMOS baseband‐active‐feedback receiver frontend with passive voltage‐commutating mixers is proposed. …”
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