Design of Shadow Filter Using Low-Voltage Multiple-Input Operational Transconductance Amplifiers by Montree Kumngern, Fabian Khateb, Tomasz Kulej, Natchayathorn Wattikornsirikul

“…The OTA and shadow filters were designed and simulated using a 0.18 µm CMOS process to validate the functionality and performance of the proposed circuits.…”
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Design of Modular Power Management and Attitude Control Subsystems for a Microsatellite by Anwar Ali, Shoaib Ahmed Khan, M. Usman Khan, Haider Ali, M. Rizwan Mughal, Jaan Praks

“…Latch-up protection systems have been designed and analyzed for CMOS-based COTS components, in order to make them suitable for space radioactive environment. …”
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Source-independent quantum random number generators with integrated silicon photonics by Yongqiang Du, Xin Hua, Zhengeng Zhao, Xiaoran Sun, Zhenrong Zhang, Xi Xiao, Kejin Wei

“…Silicon photonics demonstrates significant promise for QRNG due to its benefits in miniaturization, cost-effective device manufacturing, and compatibility with CMOS microelectronics. This study experimentally demonstrates a silicon-based discrete variable SI-QRNG. …”
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A 10 GHz Dual-Loop PLL With Active Cycle-Jitter Correction Achieving 12dB Spur and 29% Jitter Reduction by Yu-Ping Huang, Yu-Sian Lu, Wei-Zen Chen

“…An experimental prototype has been fabricated in a TSMC 40 nm CMOS process. By activating the ACJC, the spurious tones can be reduced by 12 dB when a 260MHz disturbance is injected without resort to sophisticated calibration. …”
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Cosimulation of Power and Temperature Models at the SystemC/TLM for a Soft-Core Processor by Zineb El Hariti, Abdelhakim Alali, Mohamed Sadik, Kaoutar Aamali

“…On one hand, today, due to the limited power budget imposed by the batteries, power is the limiting factor of the logic CMOS. On the other hand, the downscaling of the technology node for 65 nm and beyond, based on the International Technology Roadmap for Semiconductors (ITRS) as a reference, has not only resulted in huge energy consumption but also increased the temperature chip. …”
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A High-Speed and Low-Offset Dynamic Latch Comparator by Labonnah Farzana Rahman, Mamun Bin Ibne Reaz, Chia Chieu Yin, Mohammad Marufuzzaman, Mohammad Anisur Rahman

“…The Monte-Carlo simulation results for the designed comparator in 0.18 μm CMOS process show that the equivalent input-referred offset voltage is 720 μV with 3.44 mV standard deviation. …”
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A four‐stage yield optimization technique for analog integrated circuits using optimal computing budget allocation and evolutionary algorithms by Abbas Yaseri, Mohammad Hossein Maghami, Mehdi Radmehr

“…The yield value obtained from the simulation results for two‐stage class‐AB Operational Transconductance Amplifer (OTA) in 180 nm Complementary Metal‐Oxide‐Semiconductor (CMOS) technology is 99.85%. The proposed method has less computational effort and high accuracy than the MC‐based approaches. …”
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The Effect of Ferroelectric/Dielectric Capacitance Ratio on Short-Term Retention Characteristics of MFMIS FeFET by Junghyeon Hwang, Giuk Kim, Hongrae Joh, Jinho Ahn, Sanghun Jeon

“…This is primarily due to their compatibility with CMOS technology and reliable switching characteristics. …”
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SAR-Assisted Energy-Efficient Hybrid ADCs by Kent Edrian Lozada, Dong-Jin Chang, Dong-Ryeol Oh, Min-Jae Seo, Seung-Tak Ryu

“…The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. …”
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A Novel Compact Wideband Bandpass Filter With High Upper Stopband Rejection by Qijun Lu, Jiawei Sun, Hao Zhang, Tao Zhang, Zhangming Zhu

“…The proposed BPF is fabricated in 65 nm CMOS technology with a core area of 0.072 mm² (7.1×10^-3 λ₀²). …”
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Scaling Logic Area With Multitier Standard Cells by Florian Freye, Christian Lanius, Hossein Hashemi Shadmehri, Diana Gohringer, Tobias Gemmeke

“…While the footprint of digital complementary metal-oxide–semiconductor (CMOS) circuits has continued to decrease over the years, physical limitations for further intralayer geometric scaling become apparent. …”
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Design Techniques for Single-Ended Wireline Crosstalk Cancellation Receiver Up To 112 Gb/s by Liping Zhong, Quan Pan

“…This article introduces several techniques that enable single-ended crosstalk cancellation receivers to achieve data rates of up to 56 and 112 Gb/s per lane using four-level pulse amplitude modulation (PAM-4) in 28-nm CMOS technology. These 56 and 112 Gb/s receivers achieve a bit error rate of &#x003C;<inline-formula> <tex-math notation="LaTeX">$10{^{-}10 }$ </tex-math></inline-formula> and &#x003C;<inline-formula> <tex-math notation="LaTeX">$10{^{-}12 }$ </tex-math></inline-formula> with a single-ended channel loss of 24 and 25 dB, respectively.…”
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Design of a Novel W-Sinker RF LDMOS by Xiangming Xu, Han Yu, Jingfeng Huang, Chun Wang, Wei Ji, Zhengliang Zhou, Ying Cai, Yong Wang, Pingliang Li, Peng-Fei Wang, David Wei Zhang

“…Combined with the adoption of the techniques, like grounded shield, step gate oxide, LDD optimization, and so forth, an advanced technology for RF LDMOS based on conventional 0.35 μm CMOS technology is well established. An F+A power amplifier product with frequency range of 1.8–2.1 GHz is developed for the application of 4G LTE base station and industry leading performance is achieved. …”
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Chiral exceptional point enhanced active tuning and nonreciprocity in micro-resonators by Hwaseob Lee, Lorry Chang, Ali Kecebas, Dun Mao, Yahui Xiao, Tiantian Li, Andrea Alù, Sahin K. Özdemir, Tingyi Gu

“…Our results indicate asymmetric electro-optic modulation with up to 17 dB contrast at GHz and CMOS-compatible voltage levels. Such wafer-scale nano-manufacturing of chiral electro-optic modulators and the chiral EP-tailored tunning may facilitate new micro-resonator functionalities in quantum information processing, electromagnetic wave control, and optical interconnects.…”
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RSFQ All-Digital Programmable Multitone Generator for Quantum Applications by Joao Barbosa, Jack C. Brennan, Alessandro Casaburi, M. D. Hutchings, Alex Kirichenko, Oleg Mukhanov, Martin Weides

“…Rapid single flux quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. …”
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Ferroelectric memory: state-of-the-art manufacturing and research by D. A. Abdullaev, R. A. Milovanov, R. L. Volkov, N. I. Borgardt, A. N. Lantsev, K. A. Vorotilov, A. S. Sigov

“…The leading FRAM technology remains the 130 nm node CMOS process developed at Texas Instruments fabs. …”
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A Modified Implementation of Tristate Inverter Based Static Master-Slave Flip-Flop with Improved Power-Delay-Area Product by Kunwar Singh, Satish Chandra Tiwari, Maneesha Gupta

“…HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.…”
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Hardware Efficient Speech Enhancement With Noise Aware Multi-Target Deep Learning by Salinna Abdullah, Majid Zamani, Andreas Demosthenous

“…Mapping the design on a 65-nm CMOS process led to a chip core area of <inline-formula> <tex-math notation="LaTeX">$3.88~mm^{2}$ </tex-math></inline-formula> and a power consumption of 1.91 mW when operating at a 10 MHz clock frequency.…”
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Design and Analysis of a Blocker-Tolerant Gain-Boosted N-Path Receiver Using a Bottom-Plate Switched-Capacitor Technique by Yi Mao, Gengzhen Qi, Pui-In Mak

“…Besides that, a clock-delay technique is proposed to improve the LO non-overlap characteristics. Designed in 65-nm CMOS, the simulated results present that under an 80-MHz offset frequency, the RX scores a 29 dBm OOB-IIP3 and a -2.3 dBm B-1dB. …”
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Bottom-up fabrication of 2D Rydberg exciton arrays in cuprous oxide by Kinjol Barua, Samuel Peana, Arya Deepak Keni, Vahagn Mkhitaryan, Vladimir M. Shalaev, Yong P. Chen, Alexandra Boltasseva, Hadiseh Alaeian

“…To harness these nonlinearities for quantum applications, the confinement dimensions must match the Rydberg blockade size, which can reach several microns in Cu2O. Using a CMOS-compatible growth technique, this study demonstrates the bottom-up fabrication of site-selective arrays of Cu2O microparticles. …”
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