A Power-Efficient Soft-Output Detector for Spatial-Multiplexing MIMO Communications by Hsiao-Chi Wang, Tung-Lin Liu, Yuan-Wei Wu, Hsi-Pin Ma

“…The proposed detector, using TSMC 0.18 μm single-poly six-metal CMOS process with a core area of 1.17×1.17 mm2, provides fixed throughput of 45 Mbps in 64-QAM configuration, 120 Mbps in 16-QAM configuration, and 60 Mbps in QPSK configuration. …”
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Sub-Nanosecond Greater-Than-10-V Compact Tunable Pulse Generator for Low-Duty-Cycle High-Peak-Power Ultra-Wideband Applications by Renfeng Jin, Subrata Halder, Walter R. Curtice, James C. M. Hwang, Choi L. Law

“…The present pulse generator compares favorably with pulse generators fabricated in CMOS ICs, step-recovery diodes, or other discrete devices.…”
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An Efficient Full-Wave Electromagnetic Analysis for Capacitive Body-Coupled Communication by Muhammad Irfan Kazim, Muhammad Imran Kazim, J. Jacob Wikner

“…The estimated propagation loss has been used to investigate the link-budget requirement for designing capacitive BCC system in CMOS sub-micron technologies.…”
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Synthesis and Dielectric Studies of Monoclinic Nanosized Zirconia by I. Flavia Princess Nesamani, V. Lakshmi Prabha, Aswathy Paul, D. Nirmal

“…It is expected that both nanoscaling and the high dielectric constant of ZrO2 would be useful in replacing the low-κ SiO2 dielectric with high-κ ZrO2 for CMOS fabrication technology. The synthesized ZrO2 is subjected to impedance analysis and it exhibited a dielectric constant of 25 to find its application in short channel devices like multiple gate FinFETS and as a suitable alternative for the conventional gate oxide dielectric SiO2 with dielectric value of 3.9, which cannot survive the challenge of an end of oxide thickness ≤ 1 nm.…”
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Short startup, batteryless, self‐starting thermal energy harvesting chip working in full clock cycle by Arun Kumar Sinha, Marcio Cherem Schneider

“…This study presents a chip fabricated in 130 nm CMOS technology, designed to convert a typical 50 mV output from a TEG into 1 V. …”
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The SiD Digital ECal Based on Monolithic Active Pixel Sensors by Brau James E., Breidenbach Martin, Dragone Angelo, Habib Alexandre, Rota Lorenzo, Vassilev Mirella, Vernieri Caterina

“…The first MAPS prototype (NAPA-p1), designed by SLAC in CMOS imaging 65 nm technology, is under test. The long-term objective is a wafer-scale sensor of area 5 × 20 cm2. …”
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Evaluation of Temperature, Disturbance and Noise Effect in Full Adders Based on GDI Method by Hashem Arfavi, Seyed Mohammadali Riazi, Roozbeh Hamzehyan

“…These full adder cells were evaluated by various simulations such as supply voltage change, capacitive load change, ambient temperature change and process-voltage-temperature (PVT) changes in 45 nm CMOS technology. A noise immunity curve (NIC) was derived for full adder cells to identify better-performing full adder cells. …”
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Optical Tests on a Curve Fresnel Lens as Secondary Optics for Solar Troughs by D. Fontani, P. Sansoni, F. Francini, M. DeLucia, G. Pierucci, D. Jafrancesco

“…Focusing tests are performed, illuminating different areas of the lens with solar divergence light and acquiring images on the plane of the photocell using a CMOS camera. Concentration measurements are carried out to select the best performing samples of curve Fresnel lens. …”
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A Mixed-Signal Programmable Time-Division Power-On-Reset and Volume Control Circuit for High-Resolution Hearing-Aid SoC Application by Chengying Chen, Liming Chen, Jun Yang

“…The circuit is implemented in SMIC 0.13 μm 1P8M CMOS process. The measurement results show that, in 1 V power supply, the POR, BOR, and volume control function are accomplished. …”
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A Low-Power Streaming Speech Enhancement Accelerator for Edge Devices by Ci-Hao Wu, Tian-Sheuan Chang

“…This is achieved through a 1-D processing array, utilizing configurable SRAM addressing, thereby minimizing hardware complexities and simplifying zero skipping. Using the TSMC 40nm CMOS process, the final implementation requires merely 207.8K gates and 53.75KB SRAM. …”
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Reliability of high-performance monolayer MoS2 transistors on scaled high-κ HfO2 by Hao-Yu Lan, Shao-Heng Yang, Karim-Alexandros Kantre, Daire Cott, Rahul Tripathi, Joerg Appenzeller, Zhihong Chen

“…Elastic Recoil Detection Analysis (ERDA) indicates that hydrogen, likely from the ALD precursor, is a probable cause, highlighting the need for ALD process refinement to improve 2D FET stability for CMOS compatibility.…”
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Near-Infrared All-Silicon Photodetectors by M. Casalino, G. Coppola, M. Iodice, I. Rendina, L. Sirleto

“…The technological steps utilized to fabricate the devices allow an efficiently monolithic integration with complementary metal-oxide semiconductor (CMOS) compatible structures.…”
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Broadband Polarization-Independent Edge Couplers With High Efficiency Based on SiN-Si Dual-Stage Structure by Yang Jiang, Zhewei Zhang, Peng Liu

“…Silicon nitride (SiN) plays a critical role in silicon photonics because of its lower refractive index, low waveguide loss, broad operating bandwidth and compatibility with complementary metal oxide semiconductor (CMOS) fabrication process. Here, we propose a polarization-independent sub-wavelength grating (SWG) edge coupler with high efficiency based on SiN-Si dual-stage structure with a length of only 315.8 μm. …”
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Accuracy Improvement With Weight Mapping Strategy and Output Transformation for STT-MRAM-Based Computing-in-Memory by Xianggao Wang, Na Wei, Shifan Gao, Wenhao Wu, Yi Zhao

“…This work presents an analog computing-in-memory (CiM) macro with spin-transfer torque magnetic random access memory (STT-MRAM) and 28-nm CMOS technology. The adopted CiM bitcell uses a differential scheme and balances the input resistance to minimize the nonideal factors during multiply-accumulate (MAC) operations. …”
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A fully differential switched‐capacitor integrator based programmable resolution hybrid ADC architecture for biomedical applications by Sreenivasulu Polineni, Rekha S., M. S. Bhat

“…The proposed ADC, designed and laid out in UMC 180 nm standard CMOS technology, occupies an area of 0.228 mm2. The ADC resolution is programmable from 8‐bit to 15‐bit using a 3‐bit control bus (res[2 : 0]). …”
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Monolithic 3-D-Based Nonvolatile Associative Processor for High-Performance Energy-Efficient Computations by Esteban Garzon, Alessandro Bedoya, Marco Lanuzza, Leonid Yavits

“…The proposed architecture features two monolithic layers, with CMOS logic in the first layer and an MTJ-based content-addressable memory (CAM) array in the second layer. …”
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FPGACam: A FPGA based efficient camera interfacing architecture for real time video processing by Sayantam Sarkar, Satish S. Bhairannawar, Raja K.B.

“…In this paper, we propose an efficient FPGA‐based low cost Complementary Metal Oxide Semiconductor (CMOS) camera interfacing architecture for live video streaming and processing applications. …”
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Hybrid Hamiltonian Simulation Approach for the Analysis of Quantum Error Correction Protocol Robustness by Benjamin Gys, Lander Burgelman, Kristiaan De Greve, Georges Gielen, Francky Catthoor

“…The development of future full-scale quantum computers (QCs) not only comprises the design of good quality qubits, but also entails the design of classical complementary metal–oxide semiconductor (CMOS) control circuitry and optimized operation protocols. …”
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Spectral convolutional neural network chip for in-sensor edge computing of incoherent natural light by Kaiyu Cui, Shijie Rao, Sheng Xu, Yidong Huang, Xusheng Cai, Zhilei Huang, Yu Wang, Xue Feng, Fang Liu, Wei Zhang, Yali Li, Shengjin Wang

“…The optical convolutional layer is implemented by integrating very large-scale and pixel-aligned spectral filters on CMOS image sensor. It facilitates highly parallel spectral vector-inner products of incident incoherent natural light i.e., the direct information carrier, which empowers in-sensor optical analog computing at extremely high energy efficiency. …”
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480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications by Takashi Kawamoto, Kazuhiro Ueda, Takayuki Noto

“…Each DLL is applied to our proposed shot pulse reset technique to prevent from a harmonic lock and is applied to a voltage-controlled delay line (VCDL) with a trimming function to operate against any process voltage temperature (PVT) variations. A 90 nm CMOS process was used to fabricate our proposed clock generator. …”
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