Design and Implementation of Multiple Ring Oscillator-Based TRNG Architecture by Using ADPLL by Huirem Bharat Meitei, Manoj Kumar

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Digital Phase-Locked Loops: Exploring Different Boundaries by Yuncheng Zhang, Dingxin Xu, Kenichi Okada

Subjects: “…ADPLL…”
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An Ultra-Low-Power 2.4 GHz All-Digital Phase-Locked Loop With Injection-Locked Frequency Multiplier and Continuous Frequency Tracking by Muhammad Riaz Ur Rehman, Arash Hejazi, Imran Ali, Muhammad Asif, Seongjin Oh, Pervesh Kumar, Younggun Pu, Sang-Sun Yoo, Keum Cheol Hwang, Youngoo Yang, Yeonjae Jung, Hyungki Huh, Seokkee Kim, Joon-Mo Yoo, Kang-Yoon Lee

Subjects: “…ADPLL…”
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A–102-dBm Sensitivity Multichannel Heterodyne Wake-Up Receiver With Integrated ADPLL by Linsheng Zhang, Divya Duvvuri, Suprio Bhattacharya, Anjana Dissanayake, Xinjian Liu, Henry L. Bishop, Yaobin Zhang, Travis N. Blalock, Benton H. Calhoun, Steven M. Bowers

Subjects: “…All-digital phase-locked loop (ADPLL)…”
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Millimeter-Wave All-Digital Phase-Locked Loop Using Reference Waveform Oversampling Techniques by Teerachot Siriburanon, Chunxiao Liu, Jianglin Du, Robert Bogdan Staszewski

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Nonlinearity-Induced Spur Analysis in Fractional-<italic>N</italic> Synthesizers With &#x0394;&#x03A3; Quantization Cancellation by Yizhe Hu, Weichen Tao, Robert Bogdan Staszewski

Subjects: “…All-digital phase-locked loop (ADPLL)…”
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