A Decimal Floating-Point Accurate Scalar Product Unit with a Parallel Fixed-Point Multiplier on a Virtex-5 FPGA
Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we present a parallel decimal fixed-point multiplier designed to exploit t...
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| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Wiley
2010-01-01
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| Series: | International Journal of Reconfigurable Computing |
| Online Access: | http://dx.doi.org/10.1155/2010/357839 |
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| Summary: | Decimal Floating Point operations are important for applications that cannot tolerate errors from conversions
between binary and decimal formats, for instance, commercial, financial, and insurance applications. In this paper, we
present a parallel decimal fixed-point multiplier designed to exploit the features of Virtex-5 FPGAs. Our multiplier is based
on BCD recoding schemes, fast partial product generation, and a BCD-4221 carry save adder reduction tree. Pipeline
stages can be added to target low latency. Furthermore, we extend the multiplier with an accurate scalar product unit
for IEEE 754-2008 decimal64 data format in order to provide an important operation with least possible rounding error. Compared to a previously published work, in this paper, we improve the architecture of the accurate scalar product unit
and migrate to Virtex-5 FPGAs. This decreases the fixed-point multiplier's latency by a factor of two and the accurate
scalar product unit's latency even by a factor of five. |
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| ISSN: | 1687-7195 1687-7209 |