Edge Computing Application-Specific Integrated Circuit With Two Serial Communication Protocols and a Backpropagation Neural Network
This study developed an edge computing application-specific integrated circuit (ASIC) with two serial communication protocols, adjustable weights, and a backpropagation neural network (BPNN) for edge computing. The serial peripheral interface and I2C serial communication protocols are used in the de...
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| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IEEE
2025-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/11095715/ |
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| Summary: | This study developed an edge computing application-specific integrated circuit (ASIC) with two serial communication protocols, adjustable weights, and a backpropagation neural network (BPNN) for edge computing. The serial peripheral interface and I2C serial communication protocols are used in the developed ASIC to ensure its communication reliability. Moreover, adjustable weights are employed to achieve high edge computing performance and minimize the computational load. An Arduino development board captures sensing data and sends them to the designed ASIC through the I2C communication protocol. A 25LC640 EEPROM memory microchip is mounted externally on the ASIC and stores the BPNN model, training data, and adjustable weights. The BPNN model is constructed using the inverse transfer algorithm, and this model’s training process is optimized by employing the stochastic gradient descent method. This approach not only ensures a high learning rate but also leads to relatively few iterations. Once the training procedure is complete, the obtained weights are stored in the EEPROM. Moreover, the BPNN model can be trained on a computer or other external device and then loaded into the plug-in EEPROM directly. This design not only enhances the tunability of the model but also facilitates migration and application of the learning results among devices. The designed ASIC was fabricated through the 90-nm cell-based complementary metal–oxide–semiconductor process of Taiwan Semiconductor Manufacturing Company. According to the simulation results, the proposed ASIC has a gate count of 85526, a chip area of <inline-formula> <tex-math notation="LaTeX">$0.896\times 0.896$ </tex-math></inline-formula> mm2, and power consumption of 0.7459 mW at a voltage of 1.0 V and frequency of 20 MHz. |
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| ISSN: | 2169-3536 |