Design of generic vedic ALU using reversible logic
This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to deri...
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Elsevier
2025-04-01
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| Series: | Memories - Materials, Devices, Circuits and Systems |
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| Online Access: | http://www.sciencedirect.com/science/article/pii/S2773064625000015 |
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| author | Kanchan S. Tiwari |
| author_facet | Kanchan S. Tiwari |
| author_sort | Kanchan S. Tiwari |
| collection | DOAJ |
| description | This paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry. |
| format | Article |
| id | doaj-art-f96487bf32cc45638bd76ca48ecd75ce |
| institution | Kabale University |
| issn | 2773-0646 |
| language | English |
| publishDate | 2025-04-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Memories - Materials, Devices, Circuits and Systems |
| spelling | doaj-art-f96487bf32cc45638bd76ca48ecd75ce2025-01-28T04:15:00ZengElsevierMemories - Materials, Devices, Circuits and Systems2773-06462025-04-019100121Design of generic vedic ALU using reversible logicKanchan S. Tiwari0Department of Electronics & Telecommunication Engineering, M. E. S. Wadia College of Engineering, S. P. Pune University, Pune, Maharashtra, IndiaThis paper details the design and implementation of a low-power Generic Arithmetic Logic Unit (ALU) based on Vedic mathematics principles, constructed using reversible logic gates and implemented on an Artix-7 Field-Programmable Gate Array (FPGA).The Vedic mathematics principles are employed to derive efficient computational methods, and reversible logic is harnessed to achieve minimal power dissipation and reduced heat generation in the ALU. The proposed ALU architecture is optimized to perform fundamental arithmetic operations: addition, subtraction, multiplication, and division; as well as bitwise logical operations: AND, OR, and XOR. Vedic mathematics techniques contribute to the reduction of critical paths and garbage outputs, enhancing the overall performance of the ALU. The design is synthesized and implemented on a device Xc7a35tcpg236 belonging to Artix-7 family of FPGA, and power consumption is evaluated and compared with conventional ALU designs. Performance parameters, including power consumption and delay, were benchmarked against existing designs. The designed ALU operates at a clock frequency of 408.197 MHz, featuring a maximum combinational path delay of 4.65 ns with input voltage of 1 V. Notable is its power efficiency, which consumes a mere 42 mW, as opposed to the conventional ALU with a power consumption of 73 mW. The Vinculum based logic of reducing bigger number to smaller ones thereby simplifying calculations is also added in the design. Incorporating Vedic reversible logic with vinculum in FPGA design introduces a novel approach leveraging parallelism and pipelining for enhanced efficiency and performance. Furthermore, the FPGA-based implementation showcases the scalability of the design for higher bit-width ALUs, highlighting its potential for integration into complex digital systems. The proposed Generic low-power Vedic ALU using reversible logic opens up new opportunities for energy-efficient computing applications, such as portable devices, embedded systems, and Internet of Things (IoT) devices. The fusion of Vedic mathematics with reversible logic offers a novel approach to design efficient ALUs, contributing to the advancement of low-power and high-performance digital circuitry.http://www.sciencedirect.com/science/article/pii/S2773064625000015Artix-7 FPGALow powerGeneric vedic ALUReversible logicVedic mathematicsUrdhva-Tiryagbhyam reversible logic gates |
| spellingShingle | Kanchan S. Tiwari Design of generic vedic ALU using reversible logic Memories - Materials, Devices, Circuits and Systems Artix-7 FPGA Low power Generic vedic ALU Reversible logic Vedic mathematics Urdhva-Tiryagbhyam reversible logic gates |
| title | Design of generic vedic ALU using reversible logic |
| title_full | Design of generic vedic ALU using reversible logic |
| title_fullStr | Design of generic vedic ALU using reversible logic |
| title_full_unstemmed | Design of generic vedic ALU using reversible logic |
| title_short | Design of generic vedic ALU using reversible logic |
| title_sort | design of generic vedic alu using reversible logic |
| topic | Artix-7 FPGA Low power Generic vedic ALU Reversible logic Vedic mathematics Urdhva-Tiryagbhyam reversible logic gates |
| url | http://www.sciencedirect.com/science/article/pii/S2773064625000015 |
| work_keys_str_mv | AT kanchanstiwari designofgenericvedicaluusingreversiblelogic |