Devi, T. K., & Palaniappan, S. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates. Wiley.
Chicago Style (17th ed.) CitationDevi, T. Kalavathi, and Sakthivel Palaniappan. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates. Wiley.
MLA (9th ed.) CitationDevi, T. Kalavathi, and Sakthivel Palaniappan. An Asynchronous Low Power and High Performance VLSI Architecture for Viterbi Decoder Implemented with Quasi Delay Insensitive Templates. Wiley.
Warning: These citations may not always be 100% accurate.